Hi Mingjun,
Are you using 9 data-bits or parity? Have you tried reading the SCI Control Register 3?
I had that that same problem on the 9S08BG60 when I enabled parity. Parity used a ninth data-bit, and the SCI then required that I read the SCI Control Register 3, where the ninth bit is stored, before it would clear the receive flag. I didn't care about that bit, since the SCI handled parity, but I had to read it anyway. Here is some code:
lda SC1C3 ;read the 9th data but to help clear the interrupt
lda SC1DR ;and then get the real data byte
I found it doesn't matter which order you read the two registers, but the interrupt does not clear until you read the second one.