Hello,
Further to the comment by Tony P, the maximum allowable crystal frequency is 16 MHz - to achieve an external input frequency of 40 MHz, you would need to use an oscillator module having a square wave output.
I assume that you were intending to use FBE mode, to give a CPU clock of 40MHz, and a bus clock of 20MHz. However, it is also feasible to achieve the same CPU and bus frequencies using a lower frequency crystal (FEE mode), or using the trimmed internal reference (FEI mode).
For FEE mode, the crystal frequency would need to be a "power of two" multiple of 39.0625 kHz. A crystal frequency of 5.0MHz or 10.0MHz would be suitable.
For FEI mode, the internal reference would need to be trimmed to a frequency of 39.0625 kHz. The stability of the internal reference should be adequate for normal SCI operation.
For a baud rate of 625k, the transmission period will be 16 microseconds per byte. For a 40MHz CPU bus, this corresponds to 640 cycles. The processing time for the handling of each received byte must not exceed this value, otherwise overrun errors will occur, and data will be lost. It also means that all other interrupts would most likely need to be disabled during the SCI receive process.
Regards,
Mac