Hi tomyqg,
as lukaszadrapa mentioned in this thread mpc5748g enet d-cache you have to configure the SMPU (System Memory Protection Unit) according to the example. To only have the Rx and Tx descriptors non cachable I defined a section in Project_Settings/Linker_Files/sections.ld at the text section with this content:
/* area excluded from d-cache and i-cache via smpu */
.non_cache (NOLOAD) : ALIGN(64)
{
__NON_CACHE_START = .;
*(.lwip_descriptors);
__NON_CACHE_END = .;
} > m_data AT>m_text
Then I told the linker to put the descriptors to this section (in eth.c):
__attribute__(( aligned(64), section(".lwip_descriptors") ))
Finally the SMPU must be configured to prevent caching at this section (this is mostly copied from the example):
extern char __NON_CACHE_START; // sourced from Project_Settings/Startup_Code/sections.ld
extern char __NON_CACHE_END; // sourced fromProject_Settings/Startup_Code/sections.ld
void smpu_config(void) {
/* Ensure SMPU modules are disabled */
SMPU_0.CES0.B.GVLD = 0; /* Allow all accesses from all masters to SMPU0 */
SMPU_1.CES0.B.GVLD = 0; /* Allow all accesses from all masters to SMPU1 */
/* Create desired memory regions */
/* Region 0: From __NON_CACHE_START to __NON_CACHE_STOP disable caching
this is from the beginning of RAM to __NON_CACHE_STOP */
SMPU_1.RGD[0].WORD0.R = (uint32_t)&__NON_CACHE_START; /* Region start addr- start of SRAM */
SMPU_1.RGD[0].WORD1.R = (uint32_t)&__NON_CACHE_END; /* Region end addr- end of SRAM */
SMPU_1.RGD[0].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */
SMPU_1.RGD[0].WORD3.R = 0x00000002; /* Region non-cacheable: Cache Inhibit=2*/
SMPU_1.RGD[0].WORD4.R = 0x00000000; /* PID not included in region eval. */
SMPU_1.RGD[0].WORD5.R = 0x00000001; /* Region is valid without lock */
/* Region 1: enable caching for the rest of RAM */
SMPU_1.RGD[1].WORD0.R = (uint32_t)&__NON_CACHE_END; /* Reg start addr*/
SMPU_1.RGD[1].WORD1.R = 0x400BFFFF; /*Region end */
SMPU_1.RGD[1].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */
SMPU_1.RGD[1].WORD3.R = 0x00000000; /* Region cacheable: Cache Inhibit=0*/
SMPU_1.RGD[1].WORD4.R = 0x00000000; /* PID not included in region eval. */
SMPU_1.RGD[1].WORD5.R = 0x00000001; /* Region is valid without lock */
/* Enable all SMPU regions in module */
/* SMPU_0.CES0.B.GVLD = 1;*/ /* -- NOT USED IN CODE EXAMPLE --SMPU0 */
SMPU_1.CES0.B.GVLD = 1; /* SMPU1 is enabled */
}
I hope that helps.
Regards,
Bernhard