i.MX6DQ DDR tDS and tDH.

[satoshishimoda]

Hi community,

I have some questions about i.MX6Q DDR parameter.

Please see Table 43 in IMX6DQCEC Rev.4 and my questions below.

[Q1]

I understand tDS and tDH should be calculated as below.

tDS (total setup time) = tDS(base) + delta tDS

tDH (total hold time)  = tDH(base) + delta tDH

Actually, the values of tDS and tDH in Table 43 are larger than the following values in JEDEC standard (JESD79-3F).

tDS(base) AC175 = 25 ps

tDS(base) AC150 = 75 ps

tDS(base) AC135 = 115 ps

tDH(base) DC100 = 100ps

So I think the value in Table 43 should be used for calculation instead of JEDEC standard value.

Is this correct?

[Q2]

I could not find the condition of tDS and tDH in Table 43.

Which condition is used for Table 43? (AC175 or AC150 for tDS, DC100 for tDH?)

[Q3]

I think the tDS and tDH values are actual phase difference between DATA, DQM and DQS on i.MX6Q pad.

Is this correct?

[Q4]

Can I use the same delta tDS and delta tDH values as JEDEC standard (JESD79-3F) to calculate even though tDS(base) and tDH(base) in Table 43 is different from JEDEC standard?

This post was rejected.

Would you let me know why this post was rejected? What should I edit?

Best Regards,

Satoshi Shimoda

[preeteshrathod]

JEDEC has specification of tDS and tDH is meant for DDR3 memory and not for DDR3 controller. Hence value reported in Table 43 are not proper in terms of the way (hence DDR17 and DDR18 are not proper) that it should have been specified in the datasheet. i.MX6 Datasheet should specify parameters in this way (I will just stick to DDR17 and DDR18 parameter for this post).

DDR17: This should be Tvb (Data valid before DQS edge) or Tset-up at controller i.e. controller has to specify how much timing budget it is consuming in set-up window during write condition. This value should be more enough than set -up time at memory tDS (overall including de-rating) because resulting difference will be the timing budget available to PCB interconnect.

DDR18: This should be Tva (Data valid after DQS edge) or Thold at controller i.e. controller has to specify how much timing budget it is consuming in hold window during write condition. This value should be more enough hold time at memory tDH (overall including de-rating) and resulting difference will be another timing budget available to PCB interconnect.

You can refer to "DDR2 Case study" chapter of book "A Signal Integrity Engineer's Companion:" or "Timing Analysis and Simulation for Signal Integrity Engineers". Both book contains same chapter "DDR2 Case study". even though this related to DDR2 but still DQ-DQS timings methodology is applicable to DDR3.

I hope NXP understands this and update their datasheet with proper values.

[Yuri]

Hello,

  You are right, our recent DRAM specs practically do not provide ranges for PCB delays

to get reasonable timing budgets.

  According to information from the design team the planned changes will come later this year,

the team have stated they will provide more supporting information, potentially some simulation

model data, but nothing more detailed to provide at this time, sorry.

  General recommendations now - just to follow rules in the Design checklist.

Regards,

Yuri.

[preeteshrathod]

Hello

         I can understand that strategy is now to provide Design checklist so that system designer does not have to worry about timing. I know at-least two semi-conductor vendors who has adopted similar approach. Although it does not convince me as it takes away design flexibility if I operate DDR controller at lower frequencies still somehow I will accept this approach.

        The another reason to highlight this point is that What is the reason behind providing JEDEC specifications in DDR3 controller specification (in the new revision datasheet in Jul 2015) why DDR17 and DDR18 parameter got changed from 240ps to some JEDEC speed grade AC timings. Are these specification clear to Design team or My understanding is wrong.

you can have a look at the following datasheet which mentions DDR/DDR2 AC timing specifications on page no. 23.

http://cache.nxp.com/files/32bit/doc/data_sheet/MPC8548EEC.pdf?pspll=1

Thanks and Regards

Preetesh Rathod

[Yuri]

Hello,

The JEDEC specs may be considered as base point.

Sometimes DRAM timing specs in i.MX Datasheets are not

very detailed. Two main reasons for it :

1) device characterization requires much resources ;

2) there are design recommendations and rules for customers. 

Regards,

Yuri.

[preeteshrathod]

Hello

      I got your both points that characterizing requires much resources (however such good level of information is expected from well known semiconductor vendors like NXP) and design recommendation can be generate for customers so that customer end also work can be simplified. But still it does not explain why JEDEC specification (especially electrical timing) should be present in the DDR3 controller Datasheet when those electrical timings (Set up and Hold time) are specifically meant for DDR3 memory and why would DDR3 controller will guarantee JEDEC specified Data set up and hold time at its own pin.

      Data set up and hold time at controller (or Data Valid before and Data Valid after more appropriately) should be present for DDR17 and DDR18 respectively. Please understand that during write condition DDR3 controller is transmitting strobe as well as Data  If for some reason these data are not available then kindly remove those.

      "It does not make any sense having JEDEC specified setup and hold time in the i.MX6 datasheet". (I have been trying to get clarification/explaining my point since last 2-3 months (I had raised ticket for it on 09th Feb 2016 and even emailed to NXP application engineer) but there is no satisfactory explanation neither any kind of acceptance)).

     Kindly Consultant some Signal integrity and Timing analysis expert if my point is not convincing for NXP.

Thanks and Regards

Preetesh Rathod

[Yuri]

Hello,

  As has been mentioned, the Datasheets will be modified. But this is relatively

long process.  

Regards,

Yuri.

[preeteshrathod]

It has been 8 months since it is informed that Datasheets will be modified? Do we have any action on it? 

[Yuri]

Hello,

   Alas, I have no information about documentation changing schedule.

Regards,

Yuri.

[preeteshrathod]

Recently I happened to see one of the QorIQ Processor Electrical Specifications. P4040EC.pdf. I can say that timing parameters (on page number 65 of P4040EC.pdf) tDDKHDS,tDDKLDS are similar to DDR17 of IMX6 DDR3 timing specification and tDDKHDX,tDDKLDX are similar to DDR18 of IMX6 timing specification. These paremeters (tDDKHDS,tDDKLDS,tDDKHDX,tDDKLDX) look more consistent from timings point of view. If this is the case then why NXP should have any trouble to provide consistent timing specification for IMX6.

[Yuri · Accepted solution]

Hello !

   Please look at my comments below.

1.
> So I think the value in Table 43 should be used for calculation instead of JEDEC standard value.

>

> Is this correct?

Yes.

2.
> Which condition is used for Table 43? (AC175 or AC150 for tDS, DC100 for tDH?)

  AC175, You may look at Table 30 (DDR I/O DDR3/DDR3L Mode AC Parameters) of the Datasheet :

Vih(ac) min =  Vref + 0.175 V
Vil(ac) max =  Vref – 0.175 B

AC differential input voltage Vid(ac) min = 0.35 V.

3.
> I think the tDS and tDH values are actual phase difference between DATA, DQM and DQS on i.MX6Q pad.

>

> Is this correct ?

Yes – on i.MX6 pads.

4.
> Can I use the same delta tDS and delta tDH values as JEDEC standard (JESD79-3F) to calculate even
> though tDS(base) and tDH(base) in Table 43 is different from JEDEC standard?

Yes.

Note, the i.MX6 Datasheet relates to JESD79-3D DDR3 JEDEC standard release April, 2008.

Have a great day,
Yuri

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