About ODT setting of DDR3 DQS in i.MX6DQ.

[keitanagashima]

Dear All,

Hello. I have question about ODT setting of DDR3 DQS in i.MX6DQ.

The ODT of DDR3 DQS can set at IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS*_P.

[Q1]

The DQS ODT setting was disabled in jb4.2.2_1.0.0.

i.MX6 SABRE SD isn't using ODT on DQS line, is it?

[Q2]

If one set the this register, does ODT become active to Write and Read?

(Or, is it active only at the time of Read operation?)

Best Regards,

Keita

[art]

Q1. i.MX6 SABRE SD isn't using ODT on DQS line, is it?

A1. No. Actually, there are two sets of ODT resistors, one is configured in the

IOMUX controller in the IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS*_P registers, another is

configured within the MMDC module itself. The best practice is not to use the

IOMUXC set of ODT resistors (i.e. configure them as Disabled in IOMUXC), but use

the configuration in MMDC. So, check the ODT configuration in MMDC.

Q2. If one set the this register, does ODT become active to Write and Read?

A2. It depends on MMDC configuration, many options are available.

For more information on both questions above, please refer to the Chapter 44

"Multi Mode DDR Controller (MMDC)" of the i.MX6Dual/Quad Reference Manual document.

Have a great day,
Artur

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[keitanagashima]

Dear Artur,

Hello. Do you have any update?

Please send me your answer as soon as possible.

Best Regards,

Keita

[TheAdmiral · Accepted solution]

Hi Keita,

Artur is correct: There are two sets of resistors that can be set in on the pad cell.

One set of resistors are the pull-up/pull-down resistors that are set in the IOMUX pad setting registers. These resistors are attached outside of the driver blocks internal to the pad cell and are static (meaning that they are always set to the selection made in the IOMUX pad setting registers). The resistor selections are 100K, 47K, and 22K pull up resistors and 100K pull down. These resistors are not really ODT resistors because they are not really termination resistors: There values are much to high.

One other note: When the processor is set to LPDDR2 mode, ODT resistors and not available (not defined by the JEDEC specification). The DQS traces need to be terminated during a short space prior to a READ operation. Therefore, it is necessary to use the IOMUX pull down resistors for LPDDR2 on the DQS traces. This is the only time that these resistors should be used. The resistors will always be on, but they are such a high value that they will not interfere with a driven signal.

The other set of resistors are the true ODT resistors. These resistors are technically attached to the OUTPUT Driver portion of the pad cell, but will be only used during input operations. They are controlled with the following registers:

MMDC0_MPODTCTRL     (0x021B0818)

MMDC4_MPODTCTRL     (0x021B4818)     for x64 mode only.

Fields [18:16], [14:12], [10:8], and [6:4] select the termination value used by the processor pad cells for the associated byte lane (DQS and DQ traces, DM is not used during reads). The terminations are only applied when the PHY is conducting a Read access. This is always true, and cannot be changed. But this is the correct policy. Values of 120 Ohms and 60 Ohms are typically used.

Bit [0] controls the level of the ODT trace for the in-active CS during a Write Access (If CS0 is activated, then ODT1 is controlled). If this bit is set to '1, the ODT setting on the inactive DDR will be turned on (actual value is programmed in the Mode Register of the DDR3 device). This should always be set to '1, but if only one chip select is being used, it has no effect.

Bit [1] controls the level of the ODT trace for the active CS during a Write Access (If CS0 is activated, then ODT0 is controlled). If this bit is set to '1, the ODT setting on the active DDR will be turned on (actual value is programmed in the Mode Register of the DDR3 device). This bit should always be set to '1. You want ODT set on the DDR during a Write.

Bit [2] controls the level of the ODT trace for the in-active CS during a Read Access (If CS0 is activated, then ODT1 is controlled). If this bit is set to '1, the ODT setting on the inactive DDR will be turned on (actual value is programmed in the Mode Register of the DDR3 device). This should always be set to '1, but if only one chip select is being used, it has no effect.

Bit [3] controls the level of the ODT trace for the active CS during a Read Access (If CS0 is activated, then ODT0 is controlled). If this bit is set to '1, the ODT setting on the active DDR will be turned on (actual value is programmed in the Mode Register of the DDR3 device). This bit should always be set to '0. You do not want to terminate your source during a Read Access.

Please let me know if you have any other questions.

Cheers,

TheAdmiral​

[keitanagashima]

Dear Mark,

Hello. Thank you for your answer.

> Fields [18:16], [14:12], [10:8], and [6:4] select the termination value used by the processor pad cells for the associated byte lane

> (DQS and DQ traces, DM is not used during reads).

OK. I  got it.

I understood that MMDCx_MPODTCTRL register can control not only DQ ODT but also DQS ODT.

> MMDC4_MPODTCTRL     (0x021B4818)     for x64 mode only.

Maybe, it looks MMDC1_MPODTCTRL     (0x021B4818)     for x64 mode only.

Best Regards,

Keita

[TheAdmiral]

Hi Keita,

Let me clarify this for you:

MMDC0_MPODTCTRL (0x021B0818) controls the ODT settings for:

Byte Lane 0:   DQS0, DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7

Byte Lane 1:   DQS1, DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15

Byte Lane 2:   DQS2, DQ16, DQ17, DQ18, DQ19, DQ20, DQ21, DQ22, DQ23

Byte Lane 3:   DQS3, DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30, DQ31

MMDC1_MPODTCTRL (0x021B4818) controls the ODT settings for:

Byte Lane 4:   DQS4, DQ32, DQ33, DQ34, DQ35, DQ36, DQ37, DQ38, DQ39

Byte Lane 5:   DQS5, DQ40, DQ41, DQ42, DQ43, DQ44, DQ45, DQ46, DQ47

Byte Lane 6:   DQS6, DQ48, DQ49, DQ50, DQ51, DQ52, DQ53, DQ54, DQ55

Byte Lane 7:   DQS7, DQ56, DQ57, DQ58, DQ59, DQ60, DQ61, DQ62, DQ63

Cheers,

Mark

[keitanagashima]

Thanks Mark!

I was able to understand about ODT setting.

Best Regards,

Keita

[keitanagashima]

Dear Artur,

>The best practice is not to use the

>IOMUXC set of ODT resistors (i.e. configure them as Disabled in IOMUXC), but use

>the configuration in MMDC. So, check the ODT configuration in MMDC.

Please tell me the register to configure the ODT in MMDC.

Is MMDCx_MPODTCTRL valid the ODT for not only data line but also DQS line?

Best Regards,

Keita

[keitanagashima]

Dear Artur,

Thank you for your reply.

>A1. No. Actually, there are two sets of ODT resistors, one is configured in the

>IOMUX controller in the IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS*_P registers, another is

>configured within the MMDC module itself. The best practice is not to use the

>IOMUXC set of ODT resistors (i.e. configure them as Disabled in IOMUXC), but use

>the configuration in MMDC. So, check the ODT configuration in MMDC.

If the situation was for DQ lines, I understand your answer.

Refer to  44.12.37 MMDC PHY ODT control register (MMDCx_MPODTCTRL) in IMX6DQRM(Rev.2).

We think that the MMDCx_MPODTCTRL register for data lines.

>>Q2. If one set the this register, does ODT become active to Write and Read?

>A2. It depends on MMDC configuration, many options are available.

>For more information on both questions above, please refer to the Chapter 44

>"Multi Mode DDR Controller (MMDC)" of the i.MX6Dual/Quad Reference Manual document.

I couldn't find the register setting of DOS ODT in MMDC registers.

Best Regards,

Keita