i.MX6DL: external PCIe reference clock ENET implications

[grantfordham]

Hi,

Is anyone able to supply information regarding the impact on ENET functionality when using an external 100MHz PCIe reference clock?

The i.MX6 hardware design checklist states the following:

"PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe Gen2 compliance test.  Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL outputs  solution. One clock channel connect to i.MX6 as a reference input, please click Ref14 for reference circuit. Another clock channel should connect to PCIe connector, please contact generator vendor for detailed design guide."

There is a very useful post detailing configuration changes to support external PCIe reference clock that can be found here:  i.MX6Q: Using an external reference for PCIe. Unfortunately, this post  doesn't address the impact this has on ethernet functionality e.g. can ethernet still be used if PLL6 is bypassed? Figure 10-3 in the DL RM seems to imply that Div_enet output will be incorrect (and can't possibly ever be 125MHz).

Thanks,

Grant

[igorpadykov]

Hi Grant

you are right, with 100MHz bypassing, enet 125MHz can not be obtained,

Div_enet or CCM_ANALOG_PLL_ENET DIV_SELECT=11 - 125MHz

will produce 25 MHz for operating in MII mode.

Best regards

igor

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[grantfordham]

Thanks for the response Igor. Can you tell me whether RGMII is affected too? I think RGMII uses external 125MHz clock on ENET_REF_CLK input (ball V22) but I'm not sure if PLL6 ENET clock is needed as well?

Regards,

Grant

[igorpadykov]

I believe not, as 125MHz reference clock is provided

externally on ENET_REF_CLK.

Best regards

igor