dear Qiang li,this is my change list ,please have a check,which is so urgency for me.
aaron@bp153:~/work_place/imx6jb2/_oem_scripts$ git diff ../kernel_imx/arch/arm/configs/imx6_android_pat215_defconfig
../kernel_imx/arch/arm/mach-mx6/Kconfig
../kernel_imx/arch/arm/mach-mx6/clock.c
../kernel_imx/arch/arm/plat-mxc/include/mach/ipu-v3.h
../kernel_imx/drivers/mxc/ipu3/ipu_common.c
../kernel_imx/drivers/mxc/ipu3/ipu_disp.c
../kernel_imx/drivers/video/fbmem.c
../kernel_imx/drivers/video/mxc/mxc_dispdrv.h
../kernel_imx/drivers/video/mxc/mxc_ipuv3_fb.c
diff --git a/kernel_imx/arch/arm/configs/imx6_android_pat215_defconfig b/kernel_
index 90fe5d2..bfc0e35 100644
--- a/kernel_imx/arch/arm/configs/imx6_android_pat215_defconfig
+++ b/kernel_imx/arch/arm/configs/imx6_android_pat215_defconfig
@@ -345,6 +345,11 @@ CONFIG_USB_EHCI_ARC_H1=y
CONFIG_USB_FSL_ARC_OTG=y
# CONFIG_MX6_INTER_LDO_BYPASS is not set
CONFIG_MX6_CLK_FOR_BOOTUI_TRANS=y
+#Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel
+# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS_LCD_IPU1_DI0 is not set
+CONFIG_MX6_CLK_FOR_BOOTUI_TRANS_LVDS_IPU1_DI1=y
+# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS_HDMI_IPU2_DI0 is not set
+#Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel
CONFIG_ISP1504_MXC=y
# CONFIG_MXC_IRQ_PRIOR is not set
CONFIG_MXC_PWM=y
diff --git a/kernel_imx/arch/arm/mach-mx6/Kconfig b/kernel_imx/arch/arm/mach-mx6
index 0fafbe4..3e48a1a 100755
--- a/kernel_imx/arch/arm/mach-mx6/Kconfig
+++ b/kernel_imx/arch/arm/mach-mx6/Kconfig
@@ -338,7 +338,7 @@ config USB_EHCI_ARC_H1
config USB_FSL_ARC_OTG
tristate "FSL USB OTG support"
-
+#
config MX6_INTER_LDO_BYPASS
bool "Internal LDO in MX6Q/DL bypass"
depends on REGULATOR_PFUZE100 && CPU_FREQ_IMX && ARCH_MX6
@@ -347,16 +347,40 @@ config MX6_INTER_LDO_BYPASS
This is choosed for bypass internal LDO in MX6. If choose it, internal
LDO will replaced by external pmic regulator(e.g. pfuze100), VDDCORE
can be adjust automatically adjust by cpu frequency.
-
+#Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel
config MX6_CLK_FOR_BOOTUI_TRANS
bool "MX6 clk setting for smooth UI transtion from bootloader to kernel"
depends on MXC_IPU_V3H
- default n
+ default y
help
This is choosed to keep enable IPU related clocks and PWM clocks and
avoid setting IPU related clocks' parents when initializing clock tree
so that bootloader splashimage can transition to kernel smoothly.
+choice
+ prompt "Select Display Interface"
+
+config MX6_CLK_FOR_BOOTUI_TRANS_LCD_IPU1_DI0
+ bool "Smooth UI transtion on LCD, IPU1, DI0."
+ depends on MX6_CLK_FOR_BOOTUI_TRANS
+ help
+ This is choosed to keep enable IPU related setting on LCD panel which
+ is connected on IPU1 DI0 port..
+
+config MX6_CLK_FOR_BOOTUI_TRANS_LVDS_IPU1_DI1
+ bool "Smooth UI transtion on LVDS, IPU1, DI1."
+ depends on MX6_CLK_FOR_BOOTUI_TRANS
+ help
+ This is choosed to keep enable IPU related setting on LVDS panel which
+ is connected on IPU1 DI1 port..
+config MX6_CLK_FOR_BOOTUI_TRANS_HDMI_IPU2_DI0
+ bool "Smooth UI transtion on HDMI, IPU2, DI0."
+ depends on MX6_CLK_FOR_BOOTUI_TRANS
+ help
+ This is choosed to keep enable IPU related setting on HDMI panel which
+ is connected on IPU2 DI0 port..
+endchoice
+#Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel
config MACH_IMX_BLUETOOTH_RFKILL
tristate "i.MX Bluetooth rfkill interface support"
depends on RFKILL
diff --git a/kernel_imx/arch/arm/mach-mx6/clock.c b/kernel_imx/arch/arm/mach-mx6
index 574b142..c29d714 100644
--- a/kernel_imx/arch/arm/mach-mx6/clock.c
+++ b/kernel_imx/arch/arm/mach-mx6/clock.c
@@ -5429,13 +5429,14 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned
* to support splashimage so we should not disable the
* clock to keep the display running.
*/
+
pll3_pfd_540M.disable(&pll3_pfd_540M);
pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
#endif
}
#endif
pll4_audio_main_clk.disable(&pll4_audio_main_clk);
- pll5_video_main_clk.disable(&pll5_video_main_clk);
+ //pll5_video_main_clk.disable(&pll5_video_main_clk);
pll6_mlb150_main_clk.disable(&pll6_mlb150_main_clk);
pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
pll8_enet_main_clk.disable(&pll8_enet_main_clk);
@@ -5445,18 +5446,21 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned
/* Initialize Audio and Video PLLs to valid frequency. */
clk_set_rate(&pll4_audio_main_clk, 176000000);
- clk_set_rate(&pll5_video_main_clk, 650000000);
-
+ clk_set_rate(&pll5_video_main_clk, 650000000);
+
/*
* We don't set ipu1_di_clk[1]'s parent clock to
* pll5_video_main_clk as bootloader may need
* the parent to be ldb_di1_clk to support LVDS
* panel splashimage.
*/
- clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+// clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
- clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
+ clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
#endif
+ clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
@@ -5559,8 +5563,12 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned l
* default, so we need to enable the clocks to
* keep the display running.
*/
- 3 << MXC_CCM_CCGRx_CG7_OFFSET | /* ldb_di1_clk */
- 3 << MXC_CCM_CCGRx_CG2_OFFSET | /* ipu1_di1_clk */
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+ // 3 << MXC_CCM_CCGRx_CG7_OFFSET | /* ldb_di1_clk */
+ 3 << MXC_CCM_CCGRx_CG6_OFFSET | /* ldb_di0_clk */
+ // 3 << MXC_CCM_CCGRx_CG2_OFFSET | /* ipu1_di1_clk */
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
+ 3 << MXC_CCM_CCGRx_CG1_OFFSET | /* ipu1_di0_clk */
3 << MXC_CCM_CCGRx_CG0_OFFSET | /* ipu1_clk */
#endif
3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
@@ -5572,8 +5580,14 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned l
* so we need to enable the clock to keep the
* backlight on.
*/
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+ #if 0
(machine_is_mx6q_sabresd() ?
(3 << MXC_CCM_CCGRx_CG8_OFFSET) : 0) | /* pwm1_clk */
+ #else
+ 3 << MXC_CCM_CCGRx_CG10_OFFSET | /* pwm3_clk */
+ #endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
#endif
1 << MXC_CCM_CCGRx_CG6_OFFSET |
1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
diff --git a/kernel_imx/arch/arm/plat-mxc/include/mach/ipu-v3.h b/kernel_imx/arc
index f4f7a06..3d1316e 100755
--- a/kernel_imx/arch/arm/plat-mxc/include/mach/ipu-v3.h
+++ b/kernel_imx/arch/arm/plat-mxc/include/mach/ipu-v3.h
@@ -763,5 +763,28 @@ struct imx_ipuv3_platform_data {
*/
bool bypass_reset;
};
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+void ipu_disable_irq_late_init(struct ipu_soc *ipu, uint32_t irq);
+void ipu_clear_irq_late_init(struct ipu_soc *ipu, uint32_t irq);
+int ipu_request_irq_late_init(struct ipu_soc *ipu, uint32_t irq,
+ irqreturn_t(*handler) (int, void *),
+ uint32_t irq_flags, const char *devname, void *d
+int32_t ipu_disp_get_window_pos_late_init(struct ipu_soc *ipu, ipu_channel_t ch
+ int16_t *y_pos);
+int32_t ipu_disp_set_global_alpha_late_init(struct ipu_soc *ipu, ipu_channel_t
+ uint8_t alpha);
+int32_t ipu_disp_set_color_key_late_init(struct ipu_soc *ipu, ipu_channel_t cha
+ uint32_t colorKey);
+int32_t ipu_init_channel_late_init(struct ipu_soc *ipu, ipu_channel_t channel,
+int32_t ipu_init_channel_buffer_late_init(struct ipu_soc *ipu, ipu_channel_t ch
+ uint32_t pixel_fmt,
+ uint16_t width, uint16_t height,
+ uint32_t stride,
+ ipu_rotate_mode_t rot_mode,
+ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+ dma_addr_t phyaddr_2,
+ uint32_t u_offset, uint32_t v_offset);
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
#endif /* __MACH_IPU_V3_H_ */
diff --git a/kernel_imx/drivers/mxc/ipu3/ipu_common.c b/kernel_imx/drivers/mxc/i
index 563d532..f953975 100644
--- a/kernel_imx/drivers/mxc/ipu3/ipu_common.c
+++ b/kernel_imx/drivers/mxc/ipu3/ipu_common.c
@@ -174,8 +174,15 @@ static int __devinit ipu_clk_setup_enable(struct ipu_soc *i
* clock to damage the channel setup by
* bootloader.
*/
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (!plat_data->bypass_reset) {
+#endif
clk_enable(ipu->ipu_clk);
-
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
ipu->pixel_clk[0].parent = ipu->ipu_clk;
ipu->pixel_clk[1].parent = ipu->ipu_clk;
@@ -249,11 +256,16 @@ static int __devinit ipu_probe(struct platform_device *pde
g_ipu_hw_rev = plat_data->rev;
ipu->dev = &pdev->dev;
-
- if (!plat_data->bypass_reset)
- if (plat_data->init)
- plat_data->init(pdev->id);
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (!plat_data->bypass_reset) {
+#endif
+ if (plat_data->init)
+ plat_data->init(pdev->id);
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
ipu->irq_err = platform_get_irq(pdev, 0);
ipu->irq_sync = platform_get_irq(pdev, 1);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -275,7 +287,6 @@ static int __devinit ipu_probe(struct platform_device *pdev)
dev_err(ipu->dev, "request ERR interrupt failed\n");
goto failed_req_irq_err;
}
-
ipu_base = res->start;
/* base fixup */
if (g_ipu_hw_rev == 4) /* IPUv3H */
@@ -337,8 +348,11 @@ static int __devinit ipu_probe(struct platform_device *pdev
}
platform_set_drvdata(pdev, ipu);
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
if (!plat_data->bypass_reset) {
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
ipu_reset(ipu);
ipu_disp_init(ipu);
@@ -346,8 +360,14 @@ static int __devinit ipu_probe(struct platform_device *pdev
/* Set MCU_T to divide MCU access window into 2 */
ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
IPU_DISP_GEN);
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ } else {
+ ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
+ ipu->color_key_4rgb = true;
}
-
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
/* Set sync refresh channels and CSI->mem channel as high priority */
ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
@@ -356,10 +376,15 @@ static int __devinit ipu_probe(struct platform_device *pde
ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
-
- if (!plat_data->bypass_reset)
- clk_disable(ipu->ipu_clk);
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (!plat_data->bypass_reset) {
+#endif
+ clk_disable(ipu->ipu_clk);
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
register_ipu_device(ipu, pdev->id);
ipu->online = true;
@@ -1079,7 +1104,7 @@ int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_c
uint32_t reg;
uint32_t dma_chan;
uint32_t burst_size;
-
+ WARN_ON(1);
dma_chan = channel_2_dma(channel, type);
if (!idma_is_valid(dma_chan))
return -EINVAL;
@@ -2914,3 +2939,383 @@ static void __exit ipu_gen_uninit(void)
}
module_exit(ipu_gen_uninit);
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+int32_t ipu_init_channel_late_init(struct ipu_soc *ipu, ipu_channel_t channel,
+{
+ int ret = 0;
+ uint32_t ipu_conf;
+
+ dev_dbg(ipu->dev, "init channel = %d\n", IPU_CHAN_ID(channel));
+
+ _ipu_get(ipu);
+
+ mutex_lock(&ipu->mutex_lock);
+
+ /* Re-enable error interrupts every time a channel is initialized */
+ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
+ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
+ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
+ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
+
+ if (ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
+ dev_warn(ipu->dev, "Warning: channel already initialized %d\n",
+ IPU_CHAN_ID(channel));
+ }
+
+ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
+
+ switch (channel) {
+ case MEM_DC_SYNC:
+ if (params->mem_dc_sync.di > 1) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ipu->dc_di_assignment[1] = params->mem_dc_sync.di;
+// _ipu_dc_init(ipu, 1, params->mem_dc_sync.di,
+// params->mem_dc_sync.interlaced,
+// params->mem_dc_sync.out_pixel_fmt);
+ ipu->di_use_count[params->mem_dc_sync.di]++;
+ ipu->dc_use_count++;
+ ipu->dmfc_use_count++;
+ break;
+ case MEM_BG_SYNC:
+ if (params->mem_dp_bg_sync.di > 1) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ if (params->mem_dp_bg_sync.alpha_chan_en)
+ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+ ipu->dc_di_assignment[5] = params->mem_dp_bg_sync.di;
+// _ipu_dp_init(ipu, channel, params->mem_dp_bg_sync.in_pixel_fmt,
+// params->mem_dp_bg_sync.out_pixel_fmt);
+// _ipu_dc_init(ipu, 5, params->mem_dp_bg_sync.di,
+// params->mem_dp_bg_sync.interlaced,
+// params->mem_dp_bg_sync.out_pixel_fmt);
+ ipu->di_use_count[params->mem_dp_bg_sync.di]++;
+ ipu->dc_use_count++;
+ ipu->dp_use_count++;
+ ipu->dmfc_use_count++;
+ break;
+ case MEM_FG_SYNC:
+ _ipu_dp_init(ipu, channel, params->mem_dp_fg_sync.in_pixel_fmt,
+ params->mem_dp_fg_sync.out_pixel_fmt);
+
+ if (params->mem_dp_fg_sync.alpha_chan_en)
+ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+ ipu->dc_use_count++;
+ ipu->dp_use_count++;
+ ipu->dmfc_use_count++;
+ break;
+ default:
+ dev_err(ipu->dev, "Missing channel initialization\n");
+ break;
+ }
+
+ ipu->channel_init_mask |= 1L << IPU_CHAN_ID(channel);
+
+ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
+
+err:
+ mutex_unlock(&ipu->mutex_lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipu_init_channel_late_init);
+
+int32_t ipu_init_channel_buffer_late_init(struct ipu_soc *ipu, ipu_channel_t ch
+ ipu_buffer_t type,
+ uint32_t pixel_fmt,
+ uint16_t width, uint16_t height,
+ uint32_t stride,
+ ipu_rotate_mode_t rot_mode,
+ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+ dma_addr_t phyaddr_2,
+ uint32_t u, uint32_t v)
+{
+ uint32_t reg;
+ uint32_t dma_chan;
+ uint32_t burst_size;
+
+ dma_chan = channel_2_dma(channel, type);
+ if (!idma_is_valid(dma_chan))
+ return -EINVAL;
+ if (stride < width * bytes_per_pixel(pixel_fmt))
+ stride = width * bytes_per_pixel(pixel_fmt);
+
+ if (stride % 4) {
+ dev_err(ipu->dev,
+ "Stride not 32-bit aligned, stride = %d\n", stride);
+ return -EINVAL;
+ }
+ /* IC & IRT channels' width must be multiple of 8 pixels */
+ if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
+ && (width % 8)) {
+ dev_err(ipu->dev, "Width must be 8 pixel multiple\n");
+ return -EINVAL;
+ }
+
+ if (_ipu_is_vdi_out_chan(dma_chan) &&
+ ((width < 16) || (height < 16) || (width % 2) || (height % 4)))
+ dev_err(ipu->dev, "vdi width/height limited err\n");
+ return -EINVAL;
+ }
+
+ /* IPUv3EX and IPUv3M support triple buffer */
+ if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
+ dev_err(ipu->dev, "Chan%d doesn't support triple buffer "
+ "mode\n", dma_chan);
+ return -EINVAL;
+ }
+ if (!phyaddr_1 && phyaddr_2) {
+ dev_err(ipu->dev, "Chan%d's buf1 physical addr is NULL for "
+ "triple buffer mode\n", dma_chan);
+ return -EINVAL;
+ }
+
+ mutex_lock(&ipu->mutex_lock);
+
+ /* Build parameter memory data for DMA channel */
+ _ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, u, v
+ phyaddr_0, phyaddr_1, phyaddr_2);
+
+ /* Set correlative channel parameter of local alpha channel */
+ if ((_ipu_is_ic_graphic_chan(dma_chan) ||
+ _ipu_is_dp_graphic_chan(dma_chan)) &&
+ (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
+ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, true
+ _ipu_ch_param_set_alpha_buffer_memory(ipu, dma_chan);
+ _ipu_ch_param_set_alpha_condition_read(ipu, dma_chan);
+ /* fix alpha width as 8 and burst size as 16*/
+ _ipu_ch_params_set_alpha_width(ipu, dma_chan, 8);
+ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
+ } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
+ ipu_pixel_format_has_alpha(pixel_fmt))
+ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, fals
+
+ if (rot_mode)
+ _ipu_ch_param_set_rotation(ipu, dma_chan, rot_mode);
+
+ /* IC and ROT channels have restriction of 8 or 16 pix burst length */
+ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_vdi_out_chan(dma_chan)) {
+ if ((width % 16) == 0)
+ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
+ else
+ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
+ } else if (_ipu_is_irt_chan(dma_chan)) {
+ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
+ _ipu_ch_param_set_block_mode(ipu, dma_chan);
+ } else if (_ipu_is_dmfc_chan(dma_chan)) {
+ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
+ //_ipu_dmfc_set_wait4eot(ipu, dma_chan, width);
+ _ipu_dmfc_set_burst_size(ipu, dma_chan, burst_size);
+ }
+
+ if (_ipu_disp_chan_is_interlaced(ipu, channel) ||
+ ipu->chan_is_interlaced[dma_chan])
+ _ipu_ch_param_set_interlaced_scan(ipu, dma_chan);
+
+ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan) ||
+ _ipu_is_vdi_out_chan(dma_chan)) {
+ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
+ _ipu_ic_idma_init(ipu, dma_chan, width, height, burst_size,
+ rot_mode);
+ } else if (_ipu_is_smfc_chan(dma_chan)) {
+ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
+ if ((pixel_fmt == IPU_PIX_FMT_GENERIC) &&
+ ((_ipu_ch_param_get_bpp(ipu, dma_chan) == 5) ||
+ (_ipu_ch_param_get_bpp(ipu, dma_chan) == 3)))
+ burst_size = burst_size >> 4;
+ else
+ burst_size = burst_size >> 2;
+ _ipu_smfc_set_burst_size(ipu, channel, burst_size-1);
+ }
+
+ /* AXI-id */
+ if (idma_is_set(ipu, IDMAC_CHA_PRI, dma_chan)) {
+ unsigned reg = IDMAC_CH_LOCK_EN_1;
+ uint32_t value = 0;
+ if (cpu_is_mx53() || cpu_is_mx6q() || cpu_is_mx6dl()) {
+ _ipu_ch_param_set_axi_id(ipu, dma_chan, 0);
+ switch (dma_chan) {
+ case 5:
+ value = 0x3;
+ break;
+ case 11:
+ value = 0x3 << 2;
+ break;
+ case 12:
+ value = 0x3 << 4;
+ break;
+ case 14:
+ value = 0x3 << 6;
+ break;
+ case 15:
+ value = 0x3 << 8;
+ break;
+ case 20:
+ value = 0x3 << 10;
+ break;
+ case 21:
+ value = 0x3 << 12;
+ break;
+ case 22:
+ value = 0x3 << 14;
+ break;
+ case 23:
+ value = 0x3 << 16;
+ break;
+ case 27:
+ value = 0x3 << 18;
+ break;
+ case 28:
+ value = 0x3 << 20;
+ break;
+ case 45:
+ reg = IDMAC_CH_LOCK_EN_2;
+ value = 0x3 << 0;
+ break;
+ case 46:
+ reg = IDMAC_CH_LOCK_EN_2;
+ value = 0x3 << 2;
+ break;
+ case 47:
+ reg = IDMAC_CH_LOCK_EN_2;
+ value = 0x3 << 4;
+ break;
+ case 48:
+ reg = IDMAC_CH_LOCK_EN_2;
+ value = 0x3 << 6;
+ break;
+ case 49:
+ reg = IDMAC_CH_LOCK_EN_2;
+ value = 0x3 << 8;
+ break;
+ case 50:
+ reg = IDMAC_CH_LOCK_EN_2;
+ value = 0x3 << 10;
+ break;
+ default:
+ break;
+ }
+ value |= ipu_idmac_read(ipu, reg);
+ ipu_idmac_write(ipu, value, reg);
+ } else
+ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
+ } else {
+ if (cpu_is_mx6q() || cpu_is_mx6dl())
+ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
+ }
+
+ _ipu_ch_param_dump(ipu, dma_chan);
+
+ if (phyaddr_2 && g_ipu_hw_rev >= 2) {
+ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
+ reg &= ~idma_mask(dma_chan);
+ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
+
+ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
+ reg |= idma_mask(dma_chan);
+ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
+
+ /* Set IDMAC third buffer's cpmem number */
+ /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
+ ipu_idmac_write(ipu, 0x00444047L, IDMAC_SUB_ADDR_4);
+ ipu_idmac_write(ipu, 0x46004241L, IDMAC_SUB_ADDR_3);
+ ipu_idmac_write(ipu, 0x00000045L, IDMAC_SUB_ADDR_1);
+
+ /* Reset to buffer 0 */
+ ipu_cm_write(ipu, tri_cur_buf_mask(dma_chan),
+ IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
+ } else {
+ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
+ reg &= ~idma_mask(dma_chan);
+ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
+
+ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
+ if (phyaddr_1)
+ reg |= idma_mask(dma_chan);
+ else
+ reg &= ~idma_mask(dma_chan);
+ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
+
+ /* Reset to buffer 0 */
+ ipu_cm_write(ipu, idma_mask(dma_chan),
+ IPU_CHA_CUR_BUF(dma_chan));
+
+ }
+
+ mutex_unlock(&ipu->mutex_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipu_init_channel_buffer_late_init);
+
+void ipu_disable_irq_late_init(struct ipu_soc *ipu, uint32_t irq)
+{
+ uint32_t reg;
+ unsigned long lock_flags;
+
+ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
+
+ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
+ reg &= ~IPUIRQ_2_MASK(irq);
+ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
+
+ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_disable_irq_late_init);
+
+void ipu_clear_irq_late_init(struct ipu_soc *ipu, uint32_t irq)
+{
+ unsigned long lock_flags;
+
+ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
+
+ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
+
+ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_clear_irq_late_init);
+
+int ipu_request_irq_late_init(struct ipu_soc *ipu, uint32_t irq,
+ irqreturn_t(*handler) (int, void *),
+ uint32_t irq_flags, const char *devname, void *dev_id)
+{
+ uint32_t reg;
+ unsigned long lock_flags;
+
+ BUG_ON(irq >= IPU_IRQ_COUNT);
+
+ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
+
+ if (ipu->irq_list[irq].handler != NULL) {
+ dev_err(ipu->dev,
+ "handler already installed on irq %d\n", irq);
+ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
+ return -EINVAL;
+ }
+
+ ipu->irq_list[irq].handler = handler;
+ ipu->irq_list[irq].flags = irq_flags;
+ ipu->irq_list[irq].dev_id = dev_id;
+ ipu->irq_list[irq].name = devname;
+
+ /* clear irq stat for previous use */
+ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
+ /* disable the interrupt */
+ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
+ reg &= ~IPUIRQ_2_MASK(irq);
+ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
+
+ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(ipu_request_irq_late_init);
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
diff --git a/kernel_imx/drivers/mxc/ipu3/ipu_disp.c b/kernel_imx/drivers/mxc/ipu
index 35b7819..0b94750 100644
--- a/kernel_imx/drivers/mxc/ipu3/ipu_disp.c
+++ b/kernel_imx/drivers/mxc/ipu3/ipu_disp.c
@@ -282,6 +282,7 @@ void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int
* 1C, 2C and 6B, 6F unused;
*/
dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5)
+ printk("[aaron]********add for debug1*******\n");
dmfc_wr_chan = 0x00000090;
dmfc_dp_chan = 0x0000968a;
ipu->dmfc_size_28 = 128*4;
@@ -338,6 +339,7 @@ void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_cha
u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
if (width >= HIGH_RESOLUTION_WIDTH) {
+ printk("[aaron]:**********add for debug01*****\n");
if (dma_chan == 23)
_ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
else if (dma_chan == 28)
@@ -2110,5 +2112,135 @@ void __devinit ipu_disp_init(struct ipu_soc *ipu)
ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
ipu->color_key_4rgb = true;
_ipu_init_dc_mappings(ipu);
+ printk("[aaron]:**********add for debug00*****\n");
_ipu_dmfc_init(ipu, DMFC_NORMAL, 1);
}
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+int32_t ipu_disp_set_global_alpha_late_init(struct ipu_soc *ipu, ipu_channel_t
+ bool enable, uint8_t alpha)
+{
+ uint32_t reg;
+ uint32_t flow;
+ bool bg_chan;
+
+ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+ flow = DP_SYNC;
+ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+ flow = DP_ASYNC0;
+ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+ flow = DP_ASYNC1;
+ else
+ return -EINVAL;
+
+ if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
+ channel == MEM_BG_ASYNC1)
+ bg_chan = true;
+ else
+ bg_chan = false;
+
+ mutex_lock(&ipu->mutex_lock);
+
+ if (bg_chan) {
+ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+ } else {
+ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+ ipu_dp_write(ipu, reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+ }
+
+ if (enable) {
+ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
+ ipu_dp_write(ipu, reg | ((uint32_t) alpha << 24),
+ DP_GRAPH_WIND_CTRL(flow));
+
+ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+ ipu_dp_write(ipu, reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+ } else {
+ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+ }
+
+ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+
+ mutex_unlock(&ipu->mutex_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_global_alpha_late_init);
+
+int32_t ipu_disp_set_color_key_late_init(struct ipu_soc *ipu, ipu_channel_t cha
+ bool enable, uint32_t color_key)
+{
+ uint32_t reg, flow;
+ int y, u, v;
+ int red, green, blue;
+
+ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+ flow = DP_SYNC;
+ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+ flow = DP_ASYNC0;
+ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+ flow = DP_ASYNC1;
+ else
+ return -EINVAL;
+
+ mutex_lock(&ipu->mutex_lock);
+
+ ipu->color_key_4rgb = true;
+ /* Transform color key from rgb to yuv if CSC is enabled */
+ if (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
+ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == R
+ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == Y
+ ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == Y
+
+ dev_dbg(ipu->dev, "color key 0x%x need change to yuv fmt\n", col
+
+ red = (color_key >> 16) & 0xFF;
+ green = (color_key >> 8) & 0xFF;
+ blue = color_key & 0xFF;
+
+ y = _rgb_to_yuv(0, red, green, blue);
+ u = _rgb_to_yuv(1, red, green, blue);
+ v = _rgb_to_yuv(2, red, green, blue);
+ color_key = (y << 16) | (u << 8) | v;
+
+ ipu->color_key_4rgb = false;
+
+ dev_dbg(ipu->dev, "color key change to yuv fmt 0x%x\n", color_ke
+ }
+
+ if (enable) {
+ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
+ ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(flow));
+
+ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+ ipu_dp_write(ipu, reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+ } else {
+ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+ }
+
+ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+
+ mutex_unlock(&ipu->mutex_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_color_key_late_init);
+
+int32_t ipu_disp_get_window_pos_late_init(struct ipu_soc *ipu, ipu_channel_t ch
+ int16_t *x_pos, int16_t *y_pos)
+{
+ int ret;
+
+ mutex_lock(&ipu->mutex_lock);
+ ret = _ipu_disp_get_window_pos(ipu, channel, x_pos, y_pos);
+ mutex_unlock(&ipu->mutex_lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipu_disp_get_window_pos_late_init);
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
diff --git a/kernel_imx/drivers/video/fbmem.c b/kernel_imx/drivers/video/fbmem.c
index 7a41220..af2aafa 100644
--- a/kernel_imx/drivers/video/fbmem.c
+++ b/kernel_imx/drivers/video/fbmem.c
@@ -34,7 +34,9 @@
#include <linux/fb.h>
#include <asm/fb.h>
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#include <asm/setup.h>
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
/*
* Frame buffer device initialization and setup routines
@@ -658,12 +660,18 @@ int fb_prepare_logo(struct fb_info *info, int rotate)
int fb_show_logo(struct fb_info *info, int rotate)
{
int y;
-
- y = fb_show_logo_line(info, rotate, fb_logo.logo, 0,
- num_online_cpus());
- y = fb_show_extra_logos(info, y, rotate);
-
- return y;
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+ if (strnstr(boot_command_line, "androidboot.mode=charger", COMMAND_LINE_
+ // dont show boot logo
+ return 0;
+ }
+ else {
+ y = fb_show_logo_line(info, rotate, fb_logo.logo, 0,
+ num_online_cpus());
+ y = fb_show_extra_logos(info, y, rotate);
+ return y;
+ }
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
}
#else
int fb_prepare_logo(struct fb_info *info, int rotate) { return 0; }
@@ -1632,7 +1640,75 @@ static int do_register_framebuffer(struct fb_info *fb_inf
unlock_fb_info(fb_info);
return 0;
}
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+static int do_register_framebuffer_logo(struct fb_info *fb_info)
+{
+ int i, ret;
+ struct fb_event event;
+ struct fb_videomode mode;
+
+ if (fb_check_foreignness(fb_info))
+ return -ENOSYS;
+
+ do_remove_conflicting_framebuffers(fb_info->apertures, fb_info->fix.id,
+ fb_is_primary_device(fb_info));
+
+ if (num_registered_fb == FB_MAX)
+ return -ENXIO;
+
+ num_registered_fb++;
+ for (i = 0 ; i < FB_MAX; i++)
+ if (!registered_fb[i])
+ break;
+ fb_info->node = i;
+ atomic_set(&fb_info->count, 1);
+ mutex_init(&fb_info->lock);
+ mutex_init(&fb_info->mm_lock);
+
+ fb_info->dev = device_create(fb_class, fb_info->device,
+ MKDEV(FB_MAJOR, i), NULL, "fb%d", i);
+ if (IS_ERR(fb_info->dev)) {
+ /* Not fatal */
+ printk(KERN_WARNING "Unable to create device for framebuffer %d;
+ fb_info->dev = NULL;
+ } else
+ fb_init_device(fb_info);
+
+ if (fb_info->pixmap.addr == NULL) {
+ fb_info->pixmap.addr = kmalloc(FBPIXMAPSIZE, GFP_KERNEL);
+ if (fb_info->pixmap.addr) {
+ fb_info->pixmap.size = FBPIXMAPSIZE;
+ fb_info->pixmap.buf_align = 1;
+ fb_info->pixmap.scan_align = 1;
+ fb_info->pixmap.access_align = 32;
+ fb_info->pixmap.flags = FB_PIXMAP_DEFAULT;
+ }
+ }
+ fb_info->pixmap.offset = 0;
+
+ if (!fb_info->pixmap.blit_x)
+ fb_info->pixmap.blit_x = ~(u32)0;
+
+ if (!fb_info->pixmap.blit_y)
+ fb_info->pixmap.blit_y = ~(u32)0;
+
+ if (!fb_info->modelist.prev || !fb_info->modelist.next)
+ INIT_LIST_HEAD(&fb_info->modelist);
+
+ fb_var_to_videomode(&mode, &fb_info->var);
+ fb_add_videomode(&mode, &fb_info->modelist);
+ registered_fb[i] = fb_info;
+ event.info = fb_info;
+
+ if (!lock_fb_info(fb_info))
+ return -ENODEV;
+ //ret = fb_notifier_call_chain(FB_EVENT_FB_REGISTERED, &event);
+ printk("do_register_framebuffer_logo ret = %d\n", ret);
+ unlock_fb_info(fb_info);
+ return 0;
+}
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
static int do_unregister_framebuffer(struct fb_info *fb_info)
{
struct fb_event event;
@@ -1709,10 +1785,19 @@ register_framebuffer(struct fb_info *fb_info)
mutex_lock(®istration_lock);
ret = do_register_framebuffer(fb_info);
mutex_unlock(®istration_lock);
-
return ret;
}
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+int register_framebuffer_logo(struct fb_info *fb_info)
+{
+ int ret;
+ mutex_lock(®istration_lock);
+ ret = do_register_framebuffer_logo(fb_info);
+ mutex_unlock(®istration_lock);
+ return ret;
+}
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
/**
* unregister_framebuffer - releases a frame buffer device
* @fb_info: frame buffer info structure
diff --git a/kernel_imx/drivers/video/mxc/mxc_dispdrv.h b/kernel_imx/drivers/vid
index 9a72217..ea579ca 100644
--- a/kernel_imx/drivers/video/mxc/mxc_dispdrv.h
+++ b/kernel_imx/drivers/video/mxc/mxc_dispdrv.h
@@ -40,6 +40,13 @@ struct mxc_dispdrv_driver {
void (*disable) (struct mxc_dispdrv_handle *);
/* display driver setup function, called at early part of fb_set_par */
int (*setup) (struct mxc_dispdrv_handle *, struct fb_info *fbi);
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ /* display driver late init done. */
+ void (*late_init_done) (struct mxc_dispdrv_handle *);
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+
};
struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv)
diff --git a/kernel_imx/drivers/video/mxc/mxc_ipuv3_fb.c b/kernel_imx/drivers/vi
index 7c3e419..e0d9d4c 100644
--- a/kernel_imx/drivers/video/mxc/mxc_ipuv3_fb.c
+++ b/kernel_imx/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -51,7 +51,9 @@
#include <asm/mach-types.h>
#include <mach/ipu-v3.h>
#include "mxc_dispdrv.h"
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#define delay 0
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
/*
* Driver name
*/
@@ -76,6 +78,11 @@ struct mxcfb_info {
bool overlay;
bool alpha_chan_en;
bool late_init;
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ bool late_init_idmac_done;
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
bool first_set_par;
dma_addr_t alpha_phy_addr0;
dma_addr_t alpha_phy_addr1;
@@ -322,8 +329,20 @@ static int _setup_disp_channel1(struct fb_info *fbi)
if (mxc_fbi->alpha_chan_en)
params.mem_dp_bg_sync.alpha_chan_en = true;
}
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxc_fbi->late_init)
+ {
+ ipu_init_channel_late_init(mxc_fbi->ipu, mxc_fbi->ipu_ch, ¶m
+ }
+ else
+ {
+ ipu_init_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, ¶ms);
+ }
+#else
ipu_init_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, ¶ms);
-
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
return 0;
}
@@ -380,7 +399,61 @@ static int _setup_disp_channel2(struct fb_info *fbi)
init_completion(&mxc_fbi->alpha_flip_complete);
complete(&mxc_fbi->alpha_flip_complete);
}
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxc_fbi->late_init) {
+ mxc_fbi->cur_ipu_buf = 0;
+ retval = ipu_init_channel_buffer_late_init(mxc_fbi->ipu,
+ mxc_fbi->ipu_ch, IPU_INPUT_BUFF
+ fbi_to_pixfmt(fbi),
+ fbi->var.xres, fbi->var.yres,
+ fb_stride,
+ fbi->var.rotate,
+ base,
+ base,
+ fbi->var.accel_flags &
+ FB_ACCEL_DOUBLE_FLAG ? 0
+ 0, 0);
+ if (retval) {
+ dev_err(fbi->device,
+ "ipu_init_channel_buffer error %d\n", retval);
+ return retval;
+ }
+
+ /* update u/v offset */
+ ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+ IPU_INPUT_BUFFER,
+ fbi_to_pixfmt(fbi),
+ fr_w,
+ fr_h,
+ fr_w,
+ 0, 0,
+ fr_yoff,
+ fr_xoff);
+ if (mxc_fbi->alpha_chan_en) {
+ retval = ipu_init_channel_buffer_late_init(mxc_fbi->ipu,
+ mxc_fbi->ipu_ch,
+ IPU_ALPHA_IN_BUFFER,
+ IPU_PIX_FMT_GENERIC,
+ fbi->var.xres, fbi->var
+ fbi->var.xres,
+ fbi->var.rotate,
+ mxc_fbi->alpha_phy_addr
+ mxc_fbi->alpha_phy_addr
+ 0,
+ 0, 0);
+ if (retval) {
+ dev_err(fbi->device,
+ "ipu_init_channel_buffer error %d\n", re
+ return retval;
+ }
+ }
+ mxc_fbi->late_init_idmac_done = true;
+ } else
+ {
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
retval = ipu_init_channel_buffer(mxc_fbi->ipu,
mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
fbi_to_pixfmt(fbi),
@@ -427,14 +500,34 @@ static int _setup_disp_channel2(struct fb_info *fbi)
return retval;
}
}
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
return retval;
}
static bool mxcfb_need_to_set_par(struct fb_info *fbi)
{
struct mxcfb_info *mxc_fbi = fbi->par;
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxc_fbi->late_init) {
+ if ((mxc_fbi->cur_var.xres != fbi->var.xres) ||
+ (mxc_fbi->cur_var.yres != fbi->var.yres) ||
+ (mxc_fbi->cur_var.bits_per_pixel != fbi->var.bits_per_pi
+ mxc_fbi->late_init = false;
+ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->late_init
+ mxc_fbi->dispdrv->drv->late_init_done(mxc_fbi->d
+ return true;
+ }
+ if (mxc_fbi->late_init_idmac_done)
+ return false;
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
(fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
return true;
@@ -487,7 +580,31 @@ static int mxcfb_set_par(struct fb_info *fbi)
if (fbi->var.xres == 0 || fbi->var.yres == 0)
return 0;
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxc_fbi->late_init) {
+ if (ovfbi_enable) {
+ ov_pos_ret = ipu_disp_get_window_pos_late_init(
+ mxc_fbi_fg->ipu, mxc_fbi
+ &ov_pos_x, &ov_pos_y);
+ if (ov_pos_ret < 0)
+ dev_err(fbi->device, "Get overlay pos failed, di
+ mxc_fbi->dispdrv->drv->name);
+
+ ipu_clear_irq_late_init(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu
+ ipu_disable_irq_late_init(mxc_fbi_fg->ipu, mxc_fbi_fg->i
+ ipu_clear_irq_late_init(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu
+ ipu_disable_irq_late_init(mxc_fbi_fg->ipu, mxc_fbi_fg->i
+ }
+ ipu_clear_irq_late_init(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+ ipu_disable_irq_late_init(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+ ipu_clear_irq_late_init(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
+ ipu_disable_irq_late_init(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
+ } else
+ {
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
if (ovfbi_enable) {
ov_pos_ret = ipu_disp_get_window_pos(
mxc_fbi_fg->ipu, mxc_fbi_fg->ipu
@@ -511,7 +628,11 @@ static int mxcfb_set_par(struct fb_info *fbi)
ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
/*
* Disable IPU hsp clock if it is enabled for an
* additional time in ipu common driver.
@@ -525,7 +646,6 @@ static int mxcfb_set_par(struct fb_info *fbi)
if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
if (fbi->fix.smem_start)
mxcfb_unmap_video_memory(fbi);
-
if (mxcfb_map_video_memory(fbi) < 0)
return -ENOMEM;
}
@@ -535,9 +655,15 @@ static int mxcfb_set_par(struct fb_info *fbi)
* Clear the screen in case uboot fb pixel format is not
* the same to kernel fb pixel format.
*/
- if (mxc_fbi->late_init)
- memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (!mxc_fbi->late_init) {
+#endif
+ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
mxc_fbi->first_set_par = false;
}
@@ -604,6 +730,11 @@ static int mxcfb_set_par(struct fb_info *fbi)
_setup_disp_channel1(mxc_fbi->ovfbi);
if (!mxc_fbi->overlay) {
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (!mxc_fbi->late_init) {
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
uint32_t out_pixel_fmt;
memset(&sig_cfg, 0, sizeof(sig_cfg));
@@ -645,7 +776,11 @@ static int mxcfb_set_par(struct fb_info *fbi)
"mxcfb: Error initializing panel.\n");
return -EINVAL;
}
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
fbi->mode =
(struct fb_videomode *)fb_match_mode(&fbi->var,
&fbi->modelist);
@@ -878,7 +1013,13 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var,
bg_xres = fbi_tmp->var.xres;
bg_yres = fbi_tmp->var.yres;
}
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxc_fbi->late_init)
+ ipu_disp_get_window_pos_late_init(mxc_fbi->ipu, mxc_fbi-
+ else
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
ipu_disp_get_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, &pos_x, &
if ((var->xres + pos_x) > bg_xres)
@@ -892,8 +1033,9 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, s
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
-
- if (var->yres_virtual < var->yres)
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+ if (var->yres_virtual <= var->yres)
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
var->yres_virtual = var->yres * 3;
if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
@@ -1466,6 +1608,15 @@ static int mxcfb_blank(int blank, struct fb_info *info)
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_NORMAL:
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxc_fbi->late_init) {
+ mxc_fbi->late_init = false;
+ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->late_init
+ mxc_fbi->dispdrv->drv->late_init_done(mxc_fbi->d
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->disable)
mxc_fbi->dispdrv->drv->disable(mxc_fbi->dispdrv);
ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
@@ -2157,7 +2308,9 @@ static int mxcfb_option_setup(struct platform_device *pdev
return 0;
}
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+extern int register_framebuffer_logo(struct fb_info *fb_info);
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
static int mxcfb_register(struct fb_info *fbi)
{
struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
@@ -2187,7 +2340,46 @@ static int mxcfb_register(struct fb_info *fbi)
INIT_LIST_HEAD(&fbi->modelist);
fb_var_to_videomode(&m, &fbi->var);
fb_add_videomode(&m, &fbi->modelist);
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxcfbi->late_init) {
+ if (ipu_request_irq_late_init(mxcfbi->ipu, mxcfbi->ipu_ch_irq,
+ mxcfb_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) !=
+ dev_err(fbi->device, "Error registering EOF irq handler.
+ ret = -EBUSY;
+ goto err0;
+ }
+ if (ipu_request_irq_late_init(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq
+ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi)
+ dev_err(fbi->device, "Error registering NFACK irq handle
+ ret = -EBUSY;
+ goto err1;
+ }
+
+ if (mxcfbi->ipu_vsync_pre_irq != -1) {
+ if (ipu_request_irq_late_init(mxcfbi->ipu, mxcfbi->ipu_v
+ mxcfb_vsync_pre_irq_handler, 0,
+ MXCFB_NAME, fbi) != 0) {
+ dev_err(fbi->device, "Error registering VSYNC ir
+ "handler.\n");
+ ret = -EBUSY;
+ goto err2;
+ }
+ }
+ if (mxcfbi->ipu_alp_ch_irq != -1) {
+ if (ipu_request_irq_late_init(mxcfbi->ipu, mxcfbi->ipu_a
+ mxcfb_alpha_irq_handler, IPU_IRQF_ONESHO
+ MXCFB_NAME, fbi) != 0) {
+ dev_err(fbi->device, "Error registering alpha ir
+ "handler.\n");
+ ret = -EBUSY;
+ goto err3;
+ }
+ }
+ } else {
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq,
mxcfb_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) != 0) {
dev_err(fbi->device, "Error registering EOF irq handler.\n");
@@ -2224,7 +2416,12 @@ static int mxcfb_register(struct fb_info *fbi)
ret = -EBUSY;
goto err3;
}
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
+ printk("mxcfbi->late_init = %d\n", mxcfbi->late_init);
if (!mxcfbi->late_init) {
fbi->var.activate |= FB_ACTIVATE_FORCE;
console_lock();
@@ -2258,13 +2455,35 @@ static int mxcfb_register(struct fb_info *fbi)
_setup_disp_channel1(fbi);
ipu_enable_channel(mxcfbi->ipu, mxcfbi->ipu_ch);
console_unlock();
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ mxcfbi->cur_var = fbi->var;
+ fbi->mode =
+ (struct fb_videomode *)fb_match_mode(&fbi->var,
+ printk("mxcfbi->cur_var = %d\n", mxcfbi->cur_var
+ printk("fb_info->mode->name = %s\n", fbi->mode->
+ printk("fb_info->mode->sync = %d\n", fbi->mode->
+ printk("fb_info->mode->vmode = %d\n", fbi->mode-
+ printk("fb_info->mode->flag = %d\n", fbi->mode->
+#endif
+ mxcfbi->late_init = false;
+ goto logo;
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
}
}
ret = register_framebuffer(fbi);
if (ret < 0)
goto err6;
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+ return ret;
+logo:
+ ret = register_framebuffer_logo(fbi);
+ if (ret < 0){
+ mdelay(delay);
+ goto err6;
+ }
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
return ret;
err6:
if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
@@ -2311,6 +2530,10 @@ static int mxcfb_setup_overlay(struct platform_device *pd
struct fb_info *fbi_bg, struct resource *res)
{
struct fb_info *ovfbi;
+
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ struct ipuv3_fb_platform_data *plat_data = pdev->dev.platform_data;
+#endif
struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
struct mxcfb_info *mxcfbi_fg;
int ret = 0;
@@ -2338,7 +2561,11 @@ static int mxcfb_setup_overlay(struct platform_device *pd
mxcfbi_fg->ipu_di_pix_fmt = mxcfbi_bg->ipu_di_pix_fmt;
mxcfbi_fg->overlay = true;
mxcfbi_fg->cur_blank = mxcfbi_fg->next_blank = FB_BLANK_POWERDOWN;
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ mxcfbi_fg->late_init = plat_data->late_init;
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
/* Need dummy values until real panel is configured */
ovfbi->var.xres = 240;
ovfbi->var.yres = 320;
@@ -2427,7 +2654,12 @@ static int mxcfb_probe(struct platform_device *pdev)
spin_lock_init(&mxcfbi->lock);
mxcfbi->fbi = fbi;
mxcfbi->ipu_int_clk = plat_data->int_clk;
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
mxcfbi->late_init = plat_data->late_init;
+ mxcfbi->late_init_idmac_done = false;
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
mxcfbi->first_set_par = true;
mxcfbi->panel_width_mm = plat_data->panel_width_mm;
mxcfbi->panel_height_mm = plat_data->panel_height_mm;
@@ -2477,11 +2709,23 @@ static int mxcfb_probe(struct platform_device *pdev)
ret = mxcfb_register(fbi);
if (ret < 0)
goto mxcfb_register_failed;
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ if (mxcfbi->late_init) {
+ ipu_disp_set_global_alpha_late_init(mxcfbi->ipu, mxcfbi-
+ true, 0x80);
+ ipu_disp_set_color_key_late_init(mxcfbi->ipu, mxcfbi->ip
+ } else {
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel}*/
ipu_disp_set_global_alpha(mxcfbi->ipu, mxcfbi->ipu_ch,
true, 0x80);
ipu_disp_set_color_key(mxcfbi->ipu, mxcfbi->ipu_ch, false, 0);
-
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+ }
+#endif
+/*Qisda,Aaron.SF.Tang,20150506,add for uboot logo show to the kernel{*/
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
ret = mxcfb_setup_overlay(pdev, fbi, res);