LS1021A - QSPI Flash on ls1021atwr not found

[markusniebel]

Hello,

I try to access the Serial Flash on this Board - but no success.

SW2 [off] [off] [on] [off] [on] [on] [on] [off]

SW3 [off] [on] [on] [off] [on] [off] [off] [on]

try the U-Boot from SDK 1.7 and current mainline (2015.04-rc3) with the SD-Card config with no luck

sf probe 0:0

SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff

RCW is

CPU:   Freescale LayerScape LS1021E, Version: 1.0, (0x87081110)

Clock Configuration:

       CPU0(ARMV7):1000 MHz,

       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),

Reset Configuration Word (RCW):

       00000000: 0608000a 00000000 00000000 00000000

       00000010: 20000000 00407900 60025a00 21046000

       00000020: 00000000 00000000 00000000 01038000

       00000030: 20024800 881b1540 00000000 00000000

Thanks for support

Markus

[addiyi]

Hi Markus,

I'm using uboot for Sd built from SDK 1.7 and I was able to access the qspi,

U-Boot SPL 2014.07+ls1+g659b6a2 (Mar 04 2015 - 10:23:41)

U-Boot 2014.07+ls1+g659b6a2 (Mar 04 2015 - 10:23:41)

CPU:  Freescale LayerScape LS1021E, Version: 1.0, (0x87081110)

Clock Configuration:

      CPU0(ARMV7):1000 MHz,

      Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),

Reset Configuration Word (RCW):

      00000000: 0608000a 00000000 00000000 00000000

      00000010: 20000000 00407900 60025a00 21046000

      00000020: 00000000 00000000 00000000 01038000

      00000030: 20024800 881b1540 00000000 00000000

Board: LS1021ATWR

I2C:  ready

DRAM:  1 GiB

Using SERDES1 Protocol: 32 (0x20)

MMC:  FSL_SDHC: 0

In:    serial

Out:  serial

Err:  serial

Net:  eTSEC1 is in sgmii mode.

eTSEC2 is in sgmii mode.

eTSEC1 [PRIME], eTSEC2, eTSEC3

=>

=>

=>

=> sf probe 0 0

SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

Attached you can find uboot that I used.

[markusniebel]

Hi Adrian-Mihai,

thank you for supplying the binary image - just tried it but no luck:

U-Boot SPL 2014.07+ls1+g659b6a2 (Mar 04 2015 - 10:23:41)

U-Boot 2014.07+ls1+g659b6a2 (Mar 04 2015 - 10:23:41)

CPU:   Freescale LayerScape LS1021E, Version: 1.0, (0x87081110)

Clock Configuration:

       CPU0(ARMV7):1000 MHz,

       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),

Reset Configuration Word (RCW):

       00000000: 0608000a 00000000 00000000 00000000

       00000010: 20000000 00407900 60025a00 21046000

       00000020: 00000000 00000000 00000000 01038000

       00000030: 20024800 881b1540 00000000 00000000

Board: LS1021ATWR

I2C:   ready

DRAM:  1 GiB

Using SERDES1 Protocol: 32 (0x20)

MMC:   FSL_SDHC: 0

In:    serial

Out:   serial

Err:   serial

Net:   eTSEC1 is in sgmii mode.

eTSEC2 is in sgmii mode.

eTSEC1 [PRIME], eTSEC2, eTSEC3

=> sf probe 0 0

SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff

Failed to initialize SPI flash at 0:0

could you please share the settings of SW2/3 you are using?

Thank you

Regards

Markus Niebel

[addiyi · Accepted solution]

Hi Markus,

Find below settings for SW2/3 I used on my twr board.

SW2[1:8]=0010_0111

SW3[1:8]=0110_0001

Adrian

[markusniebel]

Hi Adrian-Mihai,

thank you - my fault was to not read the manual carefull enough SW2.5 has to be off for QSPI!

(The Doku in SDK v1.7 about SW2 Setting for SD-Card boot is misleading - the RCW in

U-Boot is for QSPI but Switch is for IFC Bus)

Regards

Markus Niebel

[sinanakman]

Markus, in addition to what I just wrote above, you

can also refer to this thread :

TWR-LS1021A: kernel crashes while booting from SD Card

Regards

Sinan Akman

[sinanakman]

Hi Markus

To have the NOR flash available out of reset you will

need to boot from NOR. For this set your SW2 :

[on] [off] [off] [off] [on] [on] [on] [on].

Alternatively you can use a recent mainline u-boot.

It support LS1021ATWR and enables NOR access.

U-boot that SDK includes does not enable NOR if

you are booting from SD.

Hope this helps.

Regards

Sinan Akman

[markusniebel]

Hi Sinan,

That's the parallel Flash on IFC - I try to access the serial NOR. This is the reason not booting from NOR and use the RCW Data for Booting from SD and enabling QSPI.

Current Mainline changed the RCW, so that IFC gets enabled and QSPI is disabled. (IFC and QSPI are mutually exlusive AFAIK)

Thank you for Help

Regards

Markus Niebel

[sinanakman]

Hi Markus

Yes you are right. I am sorry I read it too quickly and assumed you were referring to parallel NOR.

Good to see Adrian-Mihai is helping.

Regards

Sinan Akman