Running an IMX6DL @ 1Ghz

[pieterronsijn]

Hi,

I'm experimenting with a nitrogen board with an i.mx6 dl. By default the cpu frequency is set to 800 Mhz, I would like to change it to 1Ghz, which is the maximum supported frequency of the mounted component.

In order to accomplish this I've added an entry in the dcd table to adjust the DIV_SELECT in the Analog ARM PLL control Register:

     DATA 4, 0x020C8000, 0x00002054

This should set the divider to 0x54 = 84, which should bring the arm pll frequency to 24 * 84 / 2 = 1008.

This is working when I load u-boot through the usb serial interface (using imx usb loader) :

     U-Boot 2013.10 (Dec 19 2013 - 10:37:42)

     CPU:   Freescale i.MX6DL rev1.0 at 1008 MHz

     Reset cause: POR

     Board: Nitrogen6X

     DRAM:  1 GiB

     MMC:   FSL_SDHC: 0, FSL_SDHC: 1

     SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB, total 2 MiB

     auto-detected panel HDMI

     Display: HDMI (1024x768)

     In:    serial

     Out:   serial

     Err:   serial

     Net:   using phy at 6

     FEC [PRIME]

     Hit any key to stop autoboot:  0

     U-Boot >

However, when I program the same u-boot in the spi flash, the cpu fails to boot.

Any hints on how I can get the cpu booting at the requested frequency from the spi flash ?

[AnsonHuang]

Hi, Pieter

     We boot i.MX6DL with 792MHz in uboot by default, you said you want to use 996MHz, in uboot or kernel? If you mean in uboot, then I have a patch below for you, although I think it is not necessary to run uboot at 996MHz, your approach is not safe, as you can NOT just increase the PLL to 996MHz, the VDDARM, VDDSOC/PU voltage need to be increased too! If you mean in kernel, then I think you can just enable the cpufreq driver, then it should support 996MHz, the patch [PATCH] ARM: imx: enable cpufreq for i.mx6dl I did yestoday is to enable this cpufreq feature for i.MX6DL, but there is also a patch for cpufreq driver, not sure when the maintainer will apply them. Below is the patch of uboot at 996MHz for you to reference, based on imx_v2009.08 uboot.

From 6535c2cb5c9af56574c3ac760cb58db9c0b04b54 Mon Sep 17 00:00:00 2001

From: Anson Huang <b20788@freescale.com>

Date: Tue, 10 Sep 2013 11:14:54 +0800

Subject: [PATCH] Increase CPU freq to 1G in uboot.

Signed-off-by: Anson Huang <b20788@freescale.com>

---

cpu/arm_cortexa8/mx6/generic.c |    7 +++++--

1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c

index ecb196c..87e0626 100644

--- a/cpu/arm_cortexa8/mx6/generic.c

+++ b/cpu/arm_cortexa8/mx6/generic.c

@@ -125,7 +125,7 @@ static u32 __decode_pll(enum pll_clocks pll, u32 infreq)

  case CPU_PLL1:

  div = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_PLL_SYS) &

  BM_ANADIG_PLL_SYS_DIV_SELECT;

- return infreq * (div >> 1);

+ return (infreq * div) >> 1;

  case BUS_PLL2:

  div = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_PLL_528) &

  BM_ANADIG_PLL_528_DIV_SELECT;

@@ -982,6 +982,7 @@ static void check_cpu_temperature(void)

#if defined(CONFIG_DISPLAY_CPUINFO)

int print_cpuinfo(void)

{

+ clk_config(CONFIG_REF_CLK_FREQ, 996, CPU_CLK);

  printf("CPU: Freescale i.MX6 family TO%d.%d at %d MHz\n",

        (get_board_rev() & 0xFF) >> 4,

        (get_board_rev() & 0xF),

@@ -1089,7 +1090,9 @@ int arch_cpu_init(void)

  val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);

  val &= ~BM_ANADIG_REG_CORE_REG2_TRG;

  val &= ~BM_ANADIG_REG_CORE_REG1_TRG;

- val |= BF_ANADIG_REG_CORE_REG2_TRG(0x14);

+ val &= ~BM_ANADIG_REG_CORE_REG0_TRG;

+ val |= BF_ANADIG_REG_CORE_REG0_TRG(0x16);

+ val |= BF_ANADIG_REG_CORE_REG2_TRG(0x16);

  REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);

  /* Need to power down PCIe */

--

1.7.1

[tanxiaofei]

Hi Yongcai,

Your patch in uboot improved VDDARM(VDDCORE) and VDDSOC to 1.25v, VDDSOC unchanged.

But the datasheet IMX6SLCEC.pdf mentioned that VDD_SOC_CAP and VDD_PU_CAP must be equal.

What's more, 1.25v is out of the limit of VDDSOC. So, which one i should follow ?

[AnsonHuang]

Hi, xiaofei

     the datasheet was updated after my patch, you may need to follow below settings in our latest kernel for i.MX6DL, regarding to VDDPU, I think you are talking about VDDPU must be equal to VDDSOC, right? Don't worry about it, I think our uboot has turned off VDDPU, you can double check it.

24                         operating-points = <

25                                 /* kHz    uV */

26                                 996000  1275000

27                                 792000  1175000

28                                 396000  1075000

29                         >;

30                         fsl,soc-operating-points = <

31                                 /* ARM kHz      SOC-PU uV */

32                                 996000            1175000

33                                 792000            1175000

34                                 396000            1175000

35                         >;

[tanxiaofei]

Hi Yongcai,

Our OS is linux and BSP is L3.0.35_4.1.0_130816_source.tar.gz. I can't  find the file "/arch/arm/boot/dts/imx6dl.dtsi" referred in your patch.

Is it for android？ In fact, these voltages in kernel follow uboot's config. Kernel doesn't set them once again.  Is it ok to use same value in both uboot and kernel ? If not ok, how to set them in kernel ?

Another question, Can uboot display startup logo if VDDPU is turned off ?

[AnsonHuang]

Hi,,

        the dts file I sent to you is for L3.10 kernel, for your L3.0.35 kernel, you should looked into code in arch/arm/mach-mx6/cpu_op-mx6.c, there is mx6dl_cpu_op_1G structure for voltage/freq, your boot should follow this. In kernel, once you enable CPUFreq driver, cpufreq will change ARM's freq according to CPU loading, and the voltage data is from this structure.

        IPU display used VDDSOC, VDDPU is only for GPU/VPU, unless you want to use them in uboot, otherwise, you can disable VDDPU, I think our uboot already did that, you can dump anatop's register 0x20c8140 to see whether VDDPU LDO is off.

[tanxiaofei]

Hi Yongcai,

Thanks for your help. I found that the measured value of these voltages are greater than the value we set by 0.02v.

For example, i set VDDARM to 1.25v. But i the measured value is 1.269v. VDDSOC/VDDPU will be the same as VDDARM.

[carmilili]

Hi Yongcai,

     Do you know how can I change CPU frequency in kernel.My board is IMX6Q SABRE SD(MCIMX6Q-SDB).

[AnsonHuang]

Hi, Carmili

     You can "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor" to see what is the current governor you are using, if it is interactive/conservative/ondemand, then the cpu freq will be changed according to cpu's loading automatically. If you want to change it manually, you need to switch it to userspace governor by "echo userspace > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor", then "echo 792000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed" is to set it to 792M, to 996M, using 996000. To see current cpufreq, you can "cat /sys/devices/system/cpu/cpu0/cpufreq/cur_cpufreq".

[JorgeRodriguez]

Hi Yongcai,

In imx6q.dtsi I have the following:

        operating-points = <

                /* kHz    uV */

                1200000 1275000

                996000  1250000

                852000  1250000

                792000  1150000

                396000  975000

        >;

        fsl,soc-operating-points = <

                /* ARM kHz  SOC-PU uV */

                1200000       1275000

                996000        1250000

                852000        1250000

                792000        1175000

                396000        1175000

but when I try echo 852000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed,   the scaling_cur_freq jumps up to 996000 instead of the specified value.

Could you please comment on how to get operation to 852 MHz ?

Regards,
Jorge.

[AnsonHuang]

Hi, Jorge

     The 852M freq is not for every chip, just for some chips with fuse programmed to max freq = 852M, this table is for all the freq we supported, but each chip has each speed_grading setting in fuse, after kernel boot up, it will remove those unsupported setpoints according to fuse setting. So, you should cat the scaling_available_frequencies to see what setpoints your chip supports.

[carmilili]

Thank you very much.

[AnsonHuang]

You are welcome.

[pieterronsijn]

Just found out you don't need to do anything in u-boot.

Enable the imx cpu freq regulator in the kernel, make sure the device tree has the appropriate setting for the cpu (they are available in imx6q.dtsi not in imx6dl.dtsl) and you should be ok to go.

                cpu@0 {

                        compatible = "arm,cortex-a9";

                        device_type = "cpu";

                        reg = <0>;

                        next-level-cache = <&L2>;

                        operating-points = <

                                /* kHz    uV */

                                996000  1250000

                                792000  1150000

                                396000  950000

                        >;

                        clock-latency = <61036>; /* two CLK32 periods */

                        clocks = <&clks 104>, <&clks 6>, <&clks 16>,

                                <&clks 17>, <&clks 170>;

                        clock-names = "arm", "pll2_pfd2_396m", "step",

                                      "pll1_sw", "pll1_sys";

                        arm-supply = <&reg_arm>;

                        pu-supply = <&reg_pu>;

                        soc-supply = <&reg_soc>;

                };

[EricNelson]

Hi Pieter,

How's this for a coincidence?

Immediately after your message in my In-Box this morning was this one from Anson Huang:

     http://lists.infradead.org/pipermail/linux-arm-kernel/2013-December/220504.html