about Errata 7293

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alfred_liu
NXP Employee
NXP Employee


Hi, Vybrid expert

in Vybrid_1N02G, we descript 7293 as follows:

e7293: XTAL: ROM code may fail to boot and return to safe mode due to insufficient

warm up time for the crystal oscillator

Errata type: Errata

Description: On occasion the xtal oscillator may not get sufficient time to stabilize. In this case, the boot

code will jump to safe mode and will continue to operate from the internal RC clock.

Workaround: Use an external clock/oscillator module to clock to the processor, ensuring the clock signal is

stable no more than 1.2 msecs after reset is released.

so my question is:

can I understand this errata that customer MUST add a external clock/oscillator if they want to be safe ( I think it's a normal requirment)?

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

on rev 1.2 default wait time was increased to 4ms.

Delay time is clocked by SIRC. 1/32000 * 256 = 8ms counting SIRC (128kHz /4). Maximal wait time for XTAL is 8ms (SCNT = 255).

Deadline is counted by PIT counting IRC (24MHz) with deadline time 1.5 * delay time.

Please program just OSC_TUNED Bank 0, Word7, byte 3 to 0xFF.

Programming project is part of Vybrid sample code freescale.com/vybrid ( http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TWR-VF65GS10&fpsp=1&tab=Design_Tools_...)

Modify \src\projects\ocotp_fuses\ocotp_fuses.c in ocotp_fuses project. (my In attachment).

Final binary ...\build\ds5\projects\ocotp_fuses\Debug\ocotp_fuses.axf  (my binary is in attachment also)

/Jiri

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johnfielden
Contributor IV

Sorry, we've run out of time.  We have fixed the issue by using an external oscillator and not using a crystal.  We have an external microcontroller that allows us to adjust when the oscillator is turned on with respect to the Vybrid.

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

understand. Could you please at least confirm that, when boot failed then you saw bias voltage on XTAL and EXTAL pins (about 0.5V without oscillations), or there were 0V?

Please send me text of all labels on the chip. We will do local tests to be sure.

Thank you

/Jiri

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

please confirm it and send Vybrid labels or pictures.

/Jiri

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johnfielden
Contributor IV

We've confirmed before that we are using the version 1.2 part.  See my other posts.

We were able to look at the bias again, it looks exactly as it should (just like your image above), about 500mV as it starts to oscillate.

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

yes I know that you are using 1.2, but I'm looking for batch number.

Important is if the bias was there when it failed at -20°C.

Thank you

/Jiri

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johnfielden
Contributor IV

Yes, we see that exactly.

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

First of all, please notice that Tower board is designed for office (industrial) range not for -40°C to 85°C.

Tower boards were not released with rev.2 silicon - you said that you have 5 samples with 2N02G label. So I assume that boot fails at -20°C are happening on different board.

If you see XTAL bias voltage on XTAL/EXTAL pins when boot fail, than it is not Vybrid oscillator fail, which I was thinking about and which happened here at -40°C. If you see small ramp on BCTRL line, then BootROM code run correctly and the issue is somewhere else. You also said "we're seeing POR to oscillator at full swing of around 3.4ms" .

Please confirm when boot fails, than you see bias voltage on XTAL/EXTAL  pins and PLL Enable ramp on BCTRL.

The best way would be to send me your oscilloscope waveforms when boot fails (RESET, EXTAL, BCTRL and 3V3_MCU).

/Jiri

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johnfielden
Contributor IV

We see that the Tower board fails to boot at +65C.

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

I did lot of tests. One of my part was failing at -40°C, but not on -20°C like yours did. That is the reason of my question.

One part is failing in 50% of tests or all 5 pieces you have from FAE are failing?

What board you are using?

Can you send us failing part or whole board?

Maybe you can contact FAE to sent him those data if you hesitate to place it on community.

/Jiri

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

one more think. Do you see bias voltage on EXTAL and XTAL pins. On the picture it is about 0.6V on EXTAL?

pastedImage_0.png

/Jiri

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johnfielden
Contributor IV

Burning the fuse did not help.  We still fail to boot at cold about 50% of the time.  Note that if we inject an external clock we boot 100% of the time.

The vybrid was soldered down to our board.  We also replaced one on a tower board.

The board is our own design.  Based heavily on the tower.

Our temp chamber is protected against humidity with a dry nitrogen flow.

The humidity is controlled, but I don't know at what level.

What is your humidity worry?  Damage?  How are non-sealed commercial products supposed to operated then?

We are using a 12pF cap.

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johnfielden
Contributor IV

We've looked at the documentation are are confused.

Section 19.3.1 – Boot eFUSE Description (p 828)

  OSC_TUNE D[7:0] – Bank Word7 Field 31:24

  0x00 = OSC_TUNE will be filled with POR default (OSC_TUNE POR Value = 0x57)

  Non-Zero = This will become the POR OSCNT value in bootrom

Section 19.4.3 – Clocks at Boot Time (p 832)

  This section discusses how CCM_CCR[OSCNT] is used at boot time.  It says the customer can over-ride the crystal startup time.

  Wait Time = 1.5 * (CCM_CCR[OSCNT]/SIRC) 

     SIRC = 128 KHz

     With OSCNT = 255 wait time would be 1.5 * (256 / 131072) = 2.93 ms 

    With OSCNT=Default (0x57=87) wait time would be 1.5 * (88/131072) = 1.01 ms

Section 10.2.1 CCM Control Register (CCM_CCR)

This section discuss how OSCNT is used and lists the POR value.  Oscillator ready counter value.  These bits define value of 32 KHz counter, that server as counter for oscillator lock time.  This is used for oscillator lock time.  Current estimation is ~2.7 ms.  This counter will be used in ignition sequence and in wake from stop sequence if CCM_CLPCR[SBYOS] bit was defined, to notify that on-chip oscillator output is ready to use.

00000000 = count 1 cycle of 32 KHz SXOSC clock

11111111 = count 256 cycles of 32 KHz SXOSC clock

01010111 = POR = 0x57

0xFF – 0x57 = 0xA8 (168)    

Calculating time to add the additional time to the started 3 ms…   168 / 32768 = 5.12 ms  --- So that gives us ~8 ms!

If it is the OSC_TUNE D that needs to be burned, what value gives us 8ms?

What about the other fuses associated with the oscillator?  Do they need to be blown too?

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

on rev 1.2 default wait time was increased to 4ms.

Delay time is clocked by SIRC. 1/32000 * 256 = 8ms counting SIRC (128kHz /4). Maximal wait time for XTAL is 8ms (SCNT = 255).

Deadline is counted by PIT counting IRC (24MHz) with deadline time 1.5 * delay time.

Please program just OSC_TUNED Bank 0, Word7, byte 3 to 0xFF.

Programming project is part of Vybrid sample code freescale.com/vybrid ( http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TWR-VF65GS10&fpsp=1&tab=Design_Tools_...)

Modify \src\projects\ocotp_fuses\ocotp_fuses.c in ocotp_fuses project. (my In attachment).

Final binary ...\build\ds5\projects\ocotp_fuses\Debug\ocotp_fuses.axf  (my binary is in attachment also)

/Jiri

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

I did some measurements in range from 20°C down to -40°C.

IRC and SIRC are quite stable on my samples. The worst case on the worst sample -40°C was 129.7kHz SIRC and 24.52MHz IRC (on 20°C 128.64kHz and 24.32MHz).

All test were OK - our EVB board booted every time. Extending delay time will probable help you. Anyway, please check stability of your XTAL / XTAL circuit. You mentioned that your XTAL starts in 0.8ms - this is unusual fast. Please check if your capacitors are not too small (our XTAL require 12pF).

Please send me some details about measurement and your boards:

  • are Vybrid chips soldered or they are in the socked ?
  • what board you are using (AutoEVB) or our own board?
  • are board protected against humidity ?
  • was humidity measured or controlled for -20°C ?

/Jiri

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johnfielden
Contributor IV

The version register says 1.3.   But we accept that we have a newer part than v1.1.

- We see 100% ok at room temperature.

- We see 50% failures at -20C.  Our product spec doesn't go down to -40C.

From the scope, we see the Vybrid enable the crystal 3.2ms after the 3.3V rises to peak.  The oscillator starts oscillating and appears to reach full amplitude about 0.8ms later.   We didn't look at the reset line this time, but from past experience the reset is released about 600usec after 3.3V is at peak.

So, we're seeing POR to osciallator at full swing of around 3.4ms.

We have not blown any fuses on the Vybrid.  Frankly, we are scared to do so.  But, we will make an exception in this case.

We tore our test setup down and were pursuing using an oscillator instead.  But, we will change course and try the fuse option first.  We are behind schedule and can't take too much more time experimenting with the device.


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johnfielden
Contributor IV

Note: R126 is not installed.

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jiri-b36968
NXP Employee
NXP Employee

Hi John,

  • you mentioned label 2N02G which indicates revision of Vybrid rev 1.2 (latest). This Vybrid revision does not have issue e7293. It was issue only on 1N02G (rev. 1.1)
  • XTAL is enabled about 4ms ofter POR. Then there is the delay which waits to XTAL start oscillating. Check is done using internal timer driven by XTAL. Default delay time is 4ms controlled by SIRC. This time can be changed by OSC_TUNED fuse from 0 up to 8ms.
  • Important time is not starting of oscillations but time when you have stable oscillations with minimal amplitude 0.5V pp. Usually 0.8V pp. This have to occur between XTAL enable and 4ms deadline.
  • Please confirm: Booting of your modules are 100% OK on normal temperature, but 100% fail on -40°C ? At which temperature it starts failing?
  • Please confirm at -40°C with external clock source  your modules are 100% OK.
  • Possible reasons:
    • wrong oscillator bias in low temperatures. 2M2 resistor is important for setting correct bias of oscillator. Please check if bias is correctly set. You can send oscilloscope waveforms with /RESET, XTAL, EXTAL and BCTL for room temperature and for -40°C. Please note that oscilloscope probes add parasitic capacity (usually about 10pF on passive probes).
    • wrong OSC_TUNED value. Please confirm that you have not changed the value of the OSC_TUNED FUSE.
    • wrong calibration of SIRC oscillator which defines 4ms delay. You can change t by program  OSC_TUNED FUSE to 8ms delay. Fuse is located in Bank0 Word7 Field[31:24]. If you do not know how to program it, I can guide you.

/Jiri

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alfred_liu
NXP Employee
NXP Employee

Hi, Jiri

Any concolusion for this issue?

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johnfielden
Contributor IV

We did an experiment where we removed the crystal and added a coax connector to a function generator.  The generator is driving a 1.1Vpp clock out with a resistor divider setting the DC point at 0.5V (the DC point is divided from the Vybrid's 3.3V).

This means that we are driving the clock input even before the Vybrid is powered, but we are desperate at this point.  At any rate, we've had no failures to boot at cold with this setup.

The giant hundred thousand dollar function generator will negatively impact our form factor.  I would like to find an on-board solution.  Looking at available oscillators, they all seem to require more than 1 ms to start up.

What is the timing specification for Vybrid power application to oscillator stable for this latest version of the part?

We have looked extensively at the Vybrid's 3.3V and the original crystal oscillator on an o-scope.  No matter the temperature, the Vybrid doesn't apply an output to the crystal until 3.2ms after power is applied.  The crystal starts oscillating about 0.8 ms after that.   I am  confused by the 1.2 ms or 1.4ms oscillation spec.  Is the spec based on power application to the Vybrid, or, is it measured from when the Vybrid turns on the crystal.  If the spec is based on the Vybrid's 3.3V, then the part fails to even power the crystal until long after the 1.4ms has expired. 

If the spec is measured from when the Vybrid powers the crystal, then we are well within even the 1.2ms spec.  If we are meeting spec, why does it fail cold?

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alfred_liu
NXP Employee
NXP Employee

Hi, John

Does your board have 2.2M ohm resistor on XTAL?


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