HW Reset on i.MX53

[GabrielHuau]

Hi all,

I found a problem about the i.MX53 initialization code of ESDCTL (flash_header.S).

I reset in a loop with u-boot (bootcmd reset and bootdelay 0) and at a random time, the board is crashed (generally a few seconds). With the help of a LED, I found that was just after :

REG_LD_AND_STR_OP(43, 0x01c, 0x04008040)

I don't really know what does this code do, but I tried to understand the command with the Reference Manual. It seems that there is an error, because when I decode "0x04008040", the CMD is "100" so 0x4 and there is no command 0x4 ...

If I put some delay after it (a lot of nop), it seems to work (not sure).

I'm using the latest u-boot with "ENGR00155891 : Fix reboot stress test failed issue".

Could someone give some explications about the CMD 0x4 please ?

Thanks,

[yekta]

Hi

Can you attach the flash_header.S file ,with the nops in dcd file ?

Thanks

[bfac]

Edited answer: "I apologize, I made a confusion with the u-boot version, the code below (edited) only works on u-boot-2009.08, available on BSP Linux_L2.6.35_11.09.01, I have not made tests on earlier BSP versions, but I believe it should work if the same u-boot version i s maintained."

This is how my flash_header.S file looks like after adding some delay:

REG_LD_AND_STR_OP(33, 0x014, 0x01ff00db)

REG_LD_AND_STR_OP(34, 0x02c, 0x000026d2)

REG_LD_AND_STR_OP(35, 0x030, 0x009f0e21)

REG_LD_AND_STR_OP(36, 0x008, 0x12273030)

REG_LD_AND_STR_OP(37, 0x004, 0x0002002d)

REG_LD_AND_STR_OP(38, 0x01c, 0x00008032)

REG_LD_AND_STR_OP(39, 0x01c, 0x00008033)

REG_LD_AND_STR_OP(40, 0x01c, 0x00028031)

REG_LD_AND_STR_OP(41, 0x01c, 0x052080b0)

REG_LD_AND_STR_OP(42, 0x01c, 0x04008040)

   ldr r2, =500000

   1:  nop

   subs r2, r2, #1

   bcs 1b

REG_LD_AND_STR_OP(43, 0x01c, 0x0000803a)

REG_LD_AND_STR_OP(44, 0x01c, 0x0000803b)

REG_LD_AND_STR_OP(45, 0x01c, 0x00028039)

REG_LD_AND_STR_OP(46, 0x01c, 0x05208138)

REG_LD_AND_STR_OP(47, 0x01c, 0x04008048)

REG_LD_AND_STR_OP(48, 0x020, 0x00005800)

REG_LD_AND_STR_OP(49, 0x040, 0x04b80003)

REG_LD_AND_STR_OP(50, 0x058, 0x00022227)

[fabio_estevam]

Just wanted to follow-up on this topic by saying that I sent a patch to U-boot that fixes this hang issue:

http://git.denx.de/?p=u-boot.git;a=commitdiff;h=aee0013e53b339a573e2a8d66062fe87765aa3bd;hp=2d6286ab...

Regards,

Fabio Estevam

[GabrielHuau]

Ok, it seems to fit. Theses delays are not respected, I will suggest a patch to fix this issue in the mainline.

[ZeeFrench]

Hi Gabriel,

There is a missing line return in the CMD bits field description in the manual (page 1249 in rev 2) : 0x4 is ZQ calibration.

Some delays need to be respected after launching calibration, maybe this was the problem :

"The controller must keep the memory lines quiet (except for CK) for the ZQ calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256 for other ZQCL and 64 for ZQCS)."

Does it fit your number of nops ?

Regards

[GabrielHuau]

Hi,

It seems to be fixed. We have to add some delay in the SDRAM calibration. In my case, I added 500 000 nops after :

"REG_LD_AND_STR_OP(43, 0x01c, 0x04008040)". This code depend on the u-boot version, in the mainline version, they use "imximage" now.

Best regards,

[GabrielHuau]

It's available on the FreeScale u-boot repository :

http://opensource.freescale.com/git?p=imx/uboot-imx.git;a=commit;h=02922d7dae392d6c506169cc9bfd5b009...

[hitlin37]

Can you please provide me the link to ENGR00155891 : Fix reboot stress test failed issue  patch.

Regards

Suvir