Has anyone used an FTDI 2232 based JTAG probe on an IMX28?

[mikej]

Hello all,

I'm looking for an inexpensive JTAG probe that will work with the IMX28EVK and boards based on it under the OpenOCD tool. I have a Segger J-Link probe inherited from another project, but it seems unable to halt the processor on my IMX28EVK. I'd prefer to buy one that's known to work.

Thanks in advance,

Mike

[fabio_estevam]

Hi James,

Yes, please start a new group for openocd. I know of at least on mx51 board (efikamx.cfg) that is currently supported in Openocd. Haven't seen any mx53 based board supported yet, but maybe this can be a good starting point, since mx51 is also CortexA8.

Will let you know as soon as I get a RealView script for mx53qsb.

Thanks,

Fabio Estevam

[JamesRobinson]

Hi Fabio,

Patches are submitted to the git host and are under review. I hope you don't mind, I included your name in the imx28evk.cfg file seeing that you supplied the RealView script. I would love to get my imx53qsb supported. What I might suggest is that we start a new group for support of openocd. Your thoughts?

As for the mx53qsb. I have already tried plugging it in to the JTAG connector on the side. But no joy, it was complaining about the auto probe function and not seeing anything. I am going to dig a little deeper, it might be a difference in the arm9 vs cortex-A8 core..... I would love to get the RealView file from you and start the support.

Thanks,

James.

[fabio_estevam]

Hi James,

I would suggest you to post two patches at the openocd mailing list: one for adding the mx28.cfg and another one for adding the mx28evk.cfg. It is a good idea to use git send-email for submitting patches to such mailing lists.

Yes, I am interested in getting mx53qsb board also supported in OpenOCD. Would you like me to send you a RealView ICE script so that you can convert it to the OpenOCD format? There is a imx53.cfg file in openocd already, so only the mx53qsb.cfg is missing.

Thanks for your support! Really appreciated.

Regards,

Fabio Estevam

[JamesRobinson]

I was planning on submitting the changes. Do you know who I should contact over at OpenOCD. I have posted to the forum, but no answer. I will check the site again.

On a side group note. I have a i.mx53QSB kit. Do you know if that needs support also?

Thanks,

James

[fabio_estevam]

Ok, got it working now and I see U-boot in the console ;-)

I had to specify the whole path for the u-boot binary.

Are you going to submit imx28.cfg and imx28evk.cfg to OpenOCD?

If you don't have time to do this, please let me know and I would be glad to submit it and adding you in the Signed-off-by of the patches.

Thanks, James!

[fabio_estevam]

Hi James,

Ok, I managed to adapt your opeoncd.cfg to make use of signalyzer.cfg instead and now I was able to proceed.

Now I enter into U-boot directory (where u-boot file is located) and then I do:

$ telnet localhost 4444
Trying ::1...
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> imx28evk_init
Initialize mx28evk board
RCLK not supported - fallback to 1000 kHz
> load_image u-boot
couldn't open u-boot
>

Any suggestion as to why load_image is failing?

Thanks a lot!

Fabio Estevam

[fabio_estevam]

Hi James,

I am trying to follow your steps and this is what I am getting:

fabio@fabio-Latitude-E6410:~/openocd/openocd$ sudo openocd -f interface/signalyzer.cfg -f board/imx28evk.cfg
Open On-Chip Debugger 0.6.0-dev-00381-gbce7009 (2012-02-03-08:06)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
dcc downloads are enabled
imx28evk_init
Error: An adapter speed is not selected in the init script. Insert a call to adapter_khz or jtag_rclk to proceed.
in procedure 'init'

Where should I insert the call to adapter_khz or jtag_rclk ?

Thanks,

Fabio Estevam

[JamesRobinson]

Hi Fabio,

I put my imx28evk in JTAG mode.

1. I started Openocd.
2.  "telnet localhost 4444"
3.  I issued a "imx28evk_init"
4.  I did a "load_image u-boot".
5.  I did a "resume 0x41008000"

 and to my surprise, U-boot was booting the the serial.... ;-)

I then loaded DDD via apt-get and then did the following.

1. Power cycled the imx28evk.
2. I started OpenOCD
3. Started DDD with "ddd --debugger /opt/freescale/usr/local/gcc-4.4.4-glibc-2.11.1-multilib-1.0/arm-fsl-linux-gnueabi/bin/arm-fsl-linux-gnueabi-gdb"
4. in the gdb window of DDD I did  "target remote localhost:3333"
5. In a new terminal window I "telnet localhost 4444"
6. Did a "load_image u-boot"
7. Did a "step 0x41008000"
8. Went back to DDD and did a "File->Open Program" and selected u-boot.
9. I can hit "F5" and step the program or "continue" in the gdb window and run it.
10. I hit "F5" and it goes back to single step and I can step the code....

So it looks like it is working.....

James.

[fabio_estevam]

Hi James,

Looks good at first sight! Are you able to download any code (U-boot for example) and do single stepping?

FYI, I have sent mx28evk support in mainline U-boot, in case you want to try it.

Please submit mx28evk support to OpenOCD if you have a chance, so that other folks with experience on the project could review it.

I will try to setup OpenOCD here and duplicate your settings.

Thanks a lot!

Fabio Estevam

[JamesRobinson]

Ok,

Here is my attempt for a first shot....

I did a the following for building openocd with the latest on m 10.04 LTS system.

1. "sudo apt-get remove openocd" to remove my current openocd.
2. "sudo apt-get install libftdi-dev" loaded the libftdi development files.
3. "git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd" to get the latest openocd.
4. "cd openocd"
5. "./bootstrap"
6. "./configure  --prefix=/usr --enable-ft2232_libftdi"
7. "make"
8. "sudo make install"
9. "cd .."
10. "openocd"

Attached are my openocd.cfg which I had in my home directory. imx28.cfg goes in "/usr/share/openocd/scripts/target". imx28evk.cfg goes in "/usr/share/openocd/scripts/board".

I was able to start openocd, then in another terminal I did a

/opt/freescale/usr/local/gcc-4.4.4-glibc-2.11.1-multilib-1.0/arm-fsl-linux-gnueabi/bin/arm-none-linux-gnueabi-gdb --eval-command="target remote localhost:3333" u-boot

It loaded without errors as far a I can tell, but I am not an expert.

Could you guys let me know if things look funky.....

Thanks,

James

output from openocd on gdb load.

Open On-Chip Debugger 0.6.0-dev-00381-gbce7009 (2012-02-01-22:47)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
1000 kHz
Info : only one transport option; autoselect 'jtag'
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
dcc downloads are enabled
imx28evk_init
Info : clock speed 1000 kHz
Info : JTAG tap: imx28.cpu tap/device found: 0x079264f3 (mfg: 0x279, part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : imx28.cpu: hardware has 2 breakpoint/watchpoint units
Info : accepting 'gdb' connection from 3333
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600000d3 pc: 0xfffe0b00
MMU: disabled, D-Cache: disabled, I-Cache: disabled
Warn : acknowledgment received, but no packet pending

[JamesRobinson]

Thank you!

The software guys at work used RealView with a Laterback. I have experence with the files, hopefully I should have something quick.

Will keep you posted.....

James.

[fabio_estevam]

Hi James,

Below is the init script used on mx28evk with RealView ICE tool and I think it will be easy to convert it to OpenOCD syntax.

If you get some progress with mx28evk on OpenOCD, please let me know.

I have used OpenOCD several years ago with mx31/mx27pdk and now I would like to start using it again on the new boards.

Regards,

Fabio Estevam

//=============================================================================            
//init script for i.MX28 DDR2            
//=============================================================================            
wait = on            
            
//****************************            
// VDDD setting            
//****************************            
//set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e            
setmem /32     0x80044010=    0x0003F503    
setmem /32     0x80044040=    0x0002041E    
            
//****************************            
// CLOCK set up            
//****************************            
// Power up PLL0 HW_CLKCTRL_PLL0CTRL0            
setmem /32    0x80040000=    0x00020000    
// Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0            
// EMI - first set DIV_EMI to div-by-2 before programming frac divider            
setmem /32    0x800400F0 =    0x80000002    
            
            
// CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz            
setmem /32    0x800401B0=    0x92921613    
// Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR            
setmem /32    0x800401D8=    0x00040080    
// HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2            
setmem /32    0x80040060=    0x00000002    
            
//****************************            
// POWER up DCDD_VDDA (DDR2)            
//****************************            
// Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC            
setmem /32    0x80044050=    0x0000270C    
            
//****************************            
// DDR2 DCDD_VDDA            
//****************************            
// First set up pin muxing and drive strength             
// Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR            
setmem /32    0x80018008=    0xC0000000    
            
//****************************            
// EMI PAD setting            
//****************************            
// Set up drive strength for EMI pins            
setmem /32    0x80019B80 =    0x00030000    //IOMUXC_SW_PAD_CTL_GRP_CTLDS
            
// Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13            
setmem /32    0x800181A8=    0xFFFFFFFF    
setmem /32    0x800181B8=    0xFFFFFFFF    
setmem /32    0x800181C8=    0xFFFFFFFF    
setmem /32    0x800181D8=    0xFFFFFFFF    
            
//** Ungate EMI clock in CCM            
setmem /32 0x800400F0 = 0x00000002            
            
//=============================================================================            
// DDR Controller Registers            
//=============================================================================            
// Manufacturer:    Elpida        
// Device Part Number:    EDE1116AEBG        
// Clock Freq.:     200MHz        
// Density:     1Gb        
// Chip Selects:    1        
// Number of Banks:    8        
// Row address:        13        
// Column address:     10        
//=============================================================================            
setmem /32    0x800E0000=    0x00000000    
setmem /32    0x800E0040=    0x00000000    
setmem /32    0x800E0054=    0x00000000    
setmem /32    0x800E0058=    0x00000000    
setmem /32    0x800E005C=    0x00000000    
setmem /32    0x800E0060=    0x00000000    
setmem /32    0x800E0064=    0x00000000    
setmem /32    0x800E0068=    0x00010101    
setmem /32    0x800E006C=    0x01010101    
setmem /32    0x800E0070=    0x000f0f01    
setmem /32    0x800E0074=    0x0102020A    
setmem /32    0x800E007C=    0x00010101    
setmem /32    0x800E0080=    0x00000100    
setmem /32    0x800E0084=    0x00000100    
setmem /32    0x800E0088=    0x00000000    
setmem /32    0x800E008C=    0x00000002    
setmem /32    0x800E0090=    0x01010000    
setmem /32    0x800E0094=    0x07080403    
setmem /32    0x800E0098=    0x06005003    
setmem /32    0x800E009C=    0x0A0000C8    
setmem /32    0x800E00A0=    0x02009C40    
setmem /32    0x800E00A4=    0x0002030C    
setmem /32    0x800E00A8=    0x0036B009    
setmem /32    0x800E00AC=    0x031A0612    
setmem /32    0x800E00B0=    0x02030202    
setmem /32    0x800E00B4=    0x00C8001C    
setmem /32    0x800E00C0=    0x00011900    
setmem /32    0x800E00C4=    0xffff0303    
setmem /32    0x800E00C8=    0x00012100    
setmem /32    0x800E00CC=    0xffff0303    
setmem /32    0x800E00D0=    0x00012100    
setmem /32    0x800E00D4=    0xffff0303    
setmem /32    0x800E00D8=    0x00012100    
setmem /32    0x800E00DC=    0xffff0303    
setmem /32    0x800E00E0=    0x00000003    
setmem /32    0x800E00E8=    0x00000000    
setmem /32    0x800E0108=    0x00000612    
setmem /32    0x800E010C=    0x01000f02    
setmem /32    0x800E0114=    0x00000200    
setmem /32    0x800E0118=    0x00020007    
setmem /32    0x800E011C=    0xf4004a27    
setmem /32    0x800E0120=    0xf4004a27    
setmem /32    0x800E012C=    0x07400300    
setmem /32    0x800E0130=    0x07400300    
setmem /32    0x800E013C=    0x00000005    
setmem /32    0x800E0140=    0x00000000    
setmem /32    0x800E0144=    0x00000000    
setmem /32    0x800E0148=    0x01000000    
setmem /32    0x800E014C=    0x01020408    
setmem /32    0x800E0150=    0x08040201    
setmem /32    0x800E0154=    0x000f1133    
setmem /32    0x800E015C=    0x00001f04    
setmem /32    0x800E0160=    0x00001f04    
setmem /32    0x800E016C=    0x00001f04    
setmem /32    0x800E0170=    0x00001f04    
setmem /32    0x800E0288=    0x00010000    
setmem /32    0x800E028C=    0x00030404    
setmem /32    0x800E0290=    0x00000003    
setmem /32    0x800E02AC=    0x01010000    
setmem /32    0x800E02B0=    0x01000000    
setmem /32    0x800E02B4=    0x03030000    
setmem /32    0x800E02B8=    0x00010303    
setmem /32    0x800E02BC=    0x01020202    
setmem /32    0x800E02C0=    0x00000000    
setmem /32    0x800E02C4=    0x02030303    
setmem /32    0x800E02C8=    0x21002103    
setmem /32    0x800E02CC=    0x00061200    
setmem /32    0x800E02D0=    0x06120612    
setmem /32    0x800E02D4=    0x04420442    // Mode register 0 for CS1 and CS0, ok to program CS1 even if not used
setmem /32    0x800E02D8=    0x00000000    // Mode register 0 for CS2 and CS3, not supported in this processor
setmem /32    0x800E02DC=    0x00040004    // Mode register 1 for CS1 and CS0, ok to program CS1 even if not used
setmem /32    0x800E02E0=    0x00000000    // Mode register 1 for CS2 and CS3, not supported in this processor
setmem /32    0x800E02E4=    0x00000000    // Mode register 2 for CS1 and CS0, ok to program CS1 even if not used
setmem /32    0x800E02E8=    0x00000000    // Mode register 2 for CS2 and CS3, not supported in this processor
setmem /32    0x800E02EC=    0x00000000    // Mode register 3 for CS1 and CS0, ok to program CS1 even if not used
setmem /32    0x800E02F0=    0x00000000    // Mode register 3 for CS2 and CS3, not supported in this processor
setmem /32    0x800E02F4=    0xffffffff    
            
//**  start controller **//            
setmem /32    0x800E0040=    0x00000001    // bit[0]: start

[JamesRobinson]

Fabio,

I didn't think of doing that, great idea. I will also try to put together an imx28evk.cfg that would go under the board directory. This file should hold the gdb and system reset info.

I will also pull the latest OpenOCD and see what support they have in there already.

The problem I have is that I did this for a custom board based on the i.mx27. So it might take me a couple wacks at it. Does anyone have the reset code they are using with other JTAG devices. I plan on looking at the u-boot init code for this.

I.E from imx27inst.cfg

    # ========================================
    #  Configure DDR on CSD0 -- initial reset
    # ========================================
    mww 0xD8001010 0x00000008

    sleep 100

    # ========================================
    #  Configure DDR on CSD0 -- wait 5000 cycle
    # ========================================
    mww 0x10027828 0x55555555
    mww 0x10027830 0x55555555
    mww 0x10027834 0x55555555
    mww 0x10027838 0x00005005
    mww 0x1002783C 0x15555555

    mww 0xD8001010 0x00000004

Thanks,

James

[fabio_estevam]

Hi James,

Do you plan to submit the mx28 support into the OpenOCD project?

Thanks,

Fabio Estevam

James Robinson said:

Hi Michael,

I just ran a quick test with the attached imx28.cfg file. It should go in /usr/share/openocd/scripts/target. I also included my openocd.cfg that I used to test the jtag.

I started openocd from a terminal session, and then telneted to localhost on port 4444. I was able to halt and resume the processor. I also did a scan_chain and got the following.

     TapName            | Enabled |   IdCode      Expected    IrLen IrCap  IrMask Instr     
---|--------------------|---------|------------|------------|------|------|------|---------
 0 | imx28.cpu          |    Y    | 0x079264f3 | 0x079264f3 | 0x04 | 0x01 | 0x0f | 0x0c

Here is a snapshot of the openocd output....

Open On-Chip Debugger 0.3.1 (2010-01-18-14:21)
$URL$
For bug reports, read
    http://openocd.berlios.de/doc/doxygen/bugs.html
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
dcc downloads are enabled
Info : clock speed 6000 kHz
Info : JTAG tap: imx28.cpu tap/device found: 0x079264f3 (mfg: 0x279, part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : accepting 'telnet' connection from 0
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600000d3 pc: 0xc003cf84
MMU: enabled, D-Cache: enabled, I-Cache: enabled

I haven't tried setting up the reset, let me know if this is good enough for you.

James

[mikej]

James Robinson said:

Hi Michael,

I just ran a quick test with the attached imx28.cfg file. It should go in /usr/share/openocd/scripts/target. I also included my openocd.cfg that I used to test the jtag.

I started openocd from a terminal session, and then telneted to localhost on port 4444. I was able to halt and resume the processor. I also did a scan_chain and got the following.

     TapName            | Enabled |   IdCode      Expected    IrLen IrCap  IrMask Instr     
---|--------------------|---------|------------|------------|------|------|------|---------
 0 | imx28.cpu          |    Y    | 0x079264f3 | 0x079264f3 | 0x04 | 0x01 | 0x0f | 0x0c

Here is a snapshot of the openocd output....

Open On-Chip Debugger 0.3.1 (2010-01-18-14:21)
$URL$
For bug reports, read
    http://openocd.berlios.de/doc/doxygen/bugs.html
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
dcc downloads are enabled
Info : clock speed 6000 kHz
Info : JTAG tap: imx28.cpu tap/device found: 0x079264f3 (mfg: 0x279, part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : accepting 'telnet' connection from 0
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600000d3 pc: 0xc003cf84
MMU: enabled, D-Cache: enabled, I-Cache: enabled

I haven't tried setting up the reset, let me know if this is good enough for you.

James

I'm in your debt, James. I've ordered the Olimex ARM-USB-OCD. Thanks again.

[JamesRobinson]

Hi Michael,

I just ran a quick test with the attached imx28.cfg file. It should go in /usr/share/openocd/scripts/target. I also included my openocd.cfg that I used to test the jtag.

I started openocd from a terminal session, and then telneted to localhost on port 4444. I was able to halt and resume the processor. I also did a scan_chain and got the following.

     TapName            | Enabled |   IdCode      Expected    IrLen IrCap  IrMask Instr     
---|--------------------|---------|------------|------------|------|------|------|---------
 0 | imx28.cpu          |    Y    | 0x079264f3 | 0x079264f3 | 0x04 | 0x01 | 0x0f | 0x0c

Here is a snapshot of the openocd output....

Open On-Chip Debugger 0.3.1 (2010-01-18-14:21)
$URL$
For bug reports, read
    http://openocd.berlios.de/doc/doxygen/bugs.html
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
dcc downloads are enabled
Info : clock speed 6000 kHz
Info : JTAG tap: imx28.cpu tap/device found: 0x079264f3 (mfg: 0x279, part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : accepting 'telnet' connection from 0
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600000d3 pc: 0xc003cf84
MMU: enabled, D-Cache: enabled, I-Cache: enabled

I haven't tried setting up the reset, let me know if this is good enough for you.

James

[JamesRobinson]

Michael,

Before you go out and get one. Let me hook mine up the my mx28evk and make sure I can get it working with the OpenOCD and the mx28evb. I have used Ubuntu to run the system and have stayed away from windows.

The thing we will need to configure is the CPU and target board. The other step will be the setup of the the internal registers on reset. I got mine from my co-workers for our mx27 board, But we should be able to get  help from the group here if we need them. 

I will try it tonight On my mx28evk  and mx53 Quick start and let you know,

James

[mikej]

James Robinson said:

I have used the Olimex ARM-USB-OCD on a custom i.MX27 and also the i.MX27ads board. I found that it was supported very well and I used it to get Barebox up and running RAM and then out of flash.

I found it cheep and also nice in the fact that it had a built in serial port.

Hope it helps....

-JR

Thanks, James. I had been considering either the Olimex or the Signalyzer JTAG probe. I'll probably go with Olimex given your report that it actually works.

[JamesRobinson]

I have used the Olimex ARM-USB-OCD on a custom i.MX27 and also the i.MX27ads board. I found that it was supported very well and I used it to get Barebox up and running RAM and then out of flash.

I found it cheep and also nice in the fact that it had a built in serial port.

Hope it helps....

-JR

[Yuri]

Alas, I have no Segger J-Link, but I think, any JTAG tool, supporting ARM926 may be applied with i.MX28.