FlexSPI NAND FLASH - Set Page for Read

[variable_andrew]

How is it possible to provide the i.MX device (I'm on an RT1015) a way to set the current NAND FLASH page?

The root of my problem is that it appears to be necessary to set the NAND read page before reading the buffer.

The current sequence I have programmed into the FLSHA1CR2 is: 

.ARDSeqIndex = NAND_CMD_LUT_SEQ_IDX_READ_FROM_CACHE,

.ARDSeqNumber = 1,

where that LUT index goes to:

    [4 * NAND_CMD_LUT_SEQ_IDX_READ_FROM_CACHE] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 3),

    [4 * NAND_CMD_LUT_SEQ_IDX_READ_FROM_CACHE + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_SDR, kFLEXSPI_1PAD, 13, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 8),

    [4 * NAND_CMD_LUT_SEQ_IDX_READ_FROM_CACHE + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x80, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

ie - for programming the AHB system with the ReadSequence - the sequence provided only reads the current NAND FLASH Buffer (without updating it if you want to read a different page). 

If I do an ERASE on some given page (testing on page 0 address 0), and then do a read using the AHB (ie - a memcpy from 0x60000000) w/o explicitly setting the current NAND page to 0, I don't get 0xFF's back. 

If I manually set the read page and then read - I get the expected data back. 

I need to somehow create a sequence that will set the NAND page, wait until set page finishes, and then read the NAND buffer. 

I can do that via my own API read commands, but how do I tell the ARM AHB system how to do this? (my testing has shown set page takes about 100 us - checked by polling the NAND status register. 

Heads up to kerryzhou‌ - this was the actual erase issue I was having - unrelated to the other thread about frequency / voltage / etc.

[kerryzhou]

Hi variable_andrew ,

   Thanks a lot for your cooperation.

    Could you also provide these information:

1. manually set the read page and then read - I get the expected data back. 

   Please share the test result and the related code.

2. do a read using the AHB (ie - a memcpy from 0x60000000) 

   Just the same page with your mannually, please share your test result and the code.

You said: necessary to set the NAND read page before reading the buffer, please also share some code on your side.

Then I can help you to check the details.

Best Regards,

kerry

[variable_andrew]

Hi kerryzhou‌, 

Sure -

One more piece of information, I contacted the Toshiba reps and they confirmed that the Toshiba NAND FLASH requires setting the page before reading. Here is what I said when I asked if set page was required before read:

Correct.  The serial NAND buffer won’t have valid data in it until the read cell array command finishes executing correctly (assuming no uncorrectable ECC errors).

There is no autoloading of a page out of reset

And from their manual (note that you have to wait for busy after set page (AKA "Read Cell Array"):

To your questions - here is the code for both:

int testErase(uint8_t *post_erase_read_buffer, uint8_t *s_nand_program_buffer){

   status_t status;

#ifdef TEST_AHB_READ

   uint32_t flashBaseAddress = EXAMPLE_FLEXSPI_AMBA_BASE + EXAMPLE_BLOCK_TO_ERASE * BLOCK_SIZE;

#endif

   /* Erase */

   status = flexspi_nand_flash_erase_block(EXAMPLE_FLEXSPI, EXAMPLE_BLOCK_TO_ERASE * BLOCK_SIZE);

   if (status != kStatus_Success) {

       //Erase Failed

      return -1;

   }

   delay();

#ifndef TEST_AHB_READ

   status = flexspi_nand_flash_read_block(EXAMPLE_FLEXSPI, 0x00000000, (uint32_t*) &post_erase_read_buffer[0], FLASH_PAGE_SIZE);

   if (status != kStatus_Success) {

        return -1;

   }

#else

   // AHB read doesn't work until we have set page in AHB somehow...

   DCACHE_CleanInvalidateByRange(flashBaseAddress, FLASH_PAGE_SIZE);

   memcpy(post_erase_read_buffer, (void *)(flashBaseAddress), FLASH_PAGE_SIZE);

#endif

   memset(s_nand_program_buffer, 0xFFU, FLASH_PAGE_SIZE);

   if (memcmp(s_nand_program_buffer, post_erase_read_buffer, FLASH_PAGE_SIZE)) {

    //Erase Failed

        return -1;

   }

   delay();

   return 0;

}

where if i do a #define TEST_AHB_READ 1 - then it tests the AHB read, otherwise it uses the API "manual" read -note that i'm using ifNOTdefined above in the 2nd #if.

Here's the manual read block function: 

status_t flexspi_nand_flash_read_block(FLEXSPI_Type *base, uint32_t addr, uint32_t *data, uint32_t byteCount){

   status_t status;

   flexspi_transfer_t flashXfer;

   status = flexspi_nand_wait_bus_busy(base);

   if (status != kStatus_Success) {

      return status;

   }

   //set page:

   flashXfer.deviceAddress = addr & 0xFFFF8000;

   flashXfer.port = kFLEXSPI_PortA1;

   flashXfer.cmdType = kFLEXSPI_Command;

   flashXfer.SeqNumber = 1;

   flashXfer.seqIndex = NAND_CMD_LUT_SEQ_IDX_READ_PAGE;

   status = FLEXSPI_TransferBlocking(base, &flashXfer);

   if (status != kStatus_Success) {

      return status;

   }

   status = flexspi_nand_wait_bus_busy(base);

   if (status != kStatus_Success) {

      return status;

   }

   //read flash:

   flashXfer.deviceAddress = addr & 0x00007FFF;

   flashXfer.port = kFLEXSPI_PortA1;

   flashXfer.cmdType = kFLEXSPI_Read;

   flashXfer.SeqNumber = 1;

   flashXfer.seqIndex = NAND_CMD_LUT_SEQ_IDX_READ_FROM_CACHE;  

   flashXfer.data = data;

   flashXfer.dataSize = byteCount;

   status = FLEXSPI_TransferBlocking(base, &flashXfer);

   if (status != kStatus_Success) {

      return status;

   }

   status = flexspi_nand_wait_bus_busy(base);

   return status;

}

I also have a testProgram that runs after testErase. 

Results are: 

Out of reset - if i run with TEST_AHB_READ undefined, then this test passes (I read back 0xFF's). 

Out of reset - if I run with TEST_AHB_READ 1, then this test fails (might read back what was programmed in previously, etc). 

Also - if i remove the #ifndef's all together- meaning I run the manual API read command, immediately followed by the AHB read command via memcpy - then the test passes because the manual read command set the page in FLASH so that all subsequent reads are reading from the correct page. 

If I reverse the order with the #ifndef's removed - then the data loaded in my memcpy will be incorrect, but then it will be overwritten by the flexspi_nand_flash_read_block call. 

[kerryzhou]

Hi variable_andrew,

   Thanks a lot for your detail information and the effort.

   The confirmation about the set the page before read the nand flash information from Toshiba is useful.

    I have a question, if you modify your manual API read command, comment read flash, just leave the set page code, then you use the AHB to read the data, whether your test can pass or not?

Best Regards,

kerry

[variable_andrew]

Hi kerryzhou‌, 

Yes - if I just leave the set page code (plus poll the FLASH status register until busy clears) - then AHB read works. 

 --- Just an additional bit of info:  if I don't wait for FLASH busy to clear, then it won't work.

[kerryzhou]

Hi variable_andrew,

   Thanks for your updated information.

   So, if add the set page code, then AHB read works, I think you can add that code, do you mind it?

   You need to wait for the flash busy to clear, otherwise, if the flash is busy, you do the new flash operation, it will have problems.

Best Regards,

Kerry

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[variable_andrew]

Hi kerryzhou‌, 

So after completing initial setup, it's still not possible to use this NAND FLASH just via the AHB i/f. 

What affect does this have regarding booting from NAND FLASH? 

I noticed in the RM in section (iMXRT1015 Ref Manual Rev 0) - Table 8-16: that the LUT has commands for both READ FROM CACHE (cmd index 0) and READ PAGE (cmd index 5). 

Does the RT1015 boot loader also use the READ PAGE before READ FROM CACHE? 

From Table 8-10, it appears that I can load in a custom busy flag offset for the "status register", and also a page read command (what I've been calling "set page") + cache read command (what i've been calling "read page").... but it means I am required to burn in fuses in order to even test booting from NAND flash, correct?

Does this mean the RT bootloader also uses API commands to do a read as follows:

1. read page,
2. wait for busy, or wait for SPI NAND BOOT Page Read Time (listed in Table 8-10 Fuse 0x6E0[13:8]
3. Cache read

??

[kerryzhou]

Hi variable_andrew,

  Do you want to boot from the toshiba NandFlash through the flexSPI? If yes, I will help you to check from our internal side, whether the boot process already contains the read page before read from cache.

Have a great day,
Kerry

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[variable_andrew]

Hi kerryzhou‌, 

Yes - if it's possible we'd like to boot from the NAND Flash through the FlexSPI. 

If you could check on that - it'd be much appreciated!

[kerryzhou]

Hi variable_andrew,

   I have a thought, you said, the AHB read has problems because it need to add the read cell array before read buffer/

  I think, whether you can add the read cell array in the read buffer LUT, or in the LUT table, the read cell array before the read buffer LUT?

   About the boot from nand flash,  you also need to modify the lookuptable in the configuration code. you can refer to the reference manual, there has an example for Winbond W25N01GVZEIG serial nandflash.

Have a great day,
Kerry

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[variable_andrew]

Hi kerryzhou‌

I think, whether you can add the read cell array in the read buffer LUT, or in the LUT table, the read cell array before the read buffer LUT?

Can you clarify what you mean here? (Are you talking about in general - how to do AHB reads w/o manually reading cell array? Or are you talking about boot?)

If talking about AHB reads in general - Even if I change the order of the LUT to where the read cell array is before the read buff in the LUT - if I am only passing the read buffer sequence to the AHB system - how does it know to run the read cell array?

If talking about boot - in table 8-15, they have the command indexes and LUT indexes for Boot from Serial NAND, and this shows Read from Cache with a command and LUT index of 0 for both, and then read page (to cache) has a command index of 5, LUT index of 11. (I'm not sure what the command index is referring to in table 8-15?)

Regarding Boot and setting the LUT - yes, I saw this example LUT containing both page read (read cell array) and read cache (read buffer). Just wanted to confirm it was actually used in boot as it's not automatically consumed by the AHB for regular read use. 

Thanks again!

[kerryzhou]

Hi variable_andrew,

  Sorry for my misleading, please ignore my last above reply.

  Today, I help you to check this point with some of our related departments.

  In factor, your test result already demonstrate it, and your operation is also correct.

  I get this information from our related department:

  You still need to add the IP command to read the cell array before you do the IP read or the AHB read.

  This is determined by the nandflash read structure, just as the toshiba told you. The FlexSPI module can't use the AHB to read the memory directly because of this nandflash design structure.

  I also check it with our ROM team, in factor, our ROM side also do it like your test result for the flexspi nand flash, use the IP command read page at first, then wait busy, then both IP and AHB can do the read cache function.

Wish it helps you!

Have a great day,
Kerry

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[kerryzhou]

Hi variable_andrew ,

   Sorry for my later reply because of Chinese Mid-Autumn Day, I will help you check it internally, and will give you feedback later, please wait patiently, thank!

Have a great day,
Kerry

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[variable_andrew]

kerryzhou‌ - updated the category for this thread