Q: how to do PCIe compliance measurement on the Sabre SDB?
Phase Jitter on the PCIe reference clock had been see problem. Pin C7 "CLK1_N" and Pin D7 "CLK1_P" were used like on the Sabre SD.
During Compliance meassurments margin of -80% and more.... was seen.
Is there a known issue? Has someone done a similar compliance measurement on the Sabre SDB?
The PCIe TX compliance tests on i.MX6 SD boards in TK's Open Lab.
Based on the internal PLL clock, i.MX6 SD boards pass the PCIe TX compliance tests.
1, please check the capacitor on NVCC_PLL_OUT, it should no less than 10uF, 22uF is better.
2, please check if the 24MHz input crystal is good enough. 50ppm is required.
3, please check the test step:
1.1 TX Test Configuration and Procedures
Overview of Test Steps
1. Integrate the patch for PCIE test to mainline, recompile the Kernel , and replace the old image of the board under test.
· Make sure the following configuration has been set, when re-compiling the kernel image.
# MX6 Options:
2. Correctly set up the test environment:
· Connect the compliance load board (CLB x1/x16) revision 2.0 into the slot of DUT, and change the switch and jumpers to select x1 .
· Connect the lane under test to oscilloscope via differential probe and matched coaxial , do remember that cable calibration should be done before test.
· Connect the clock signal to the oscilloscope. The clock must have SSC enabled or disabled to be consistent with settings for the system during normal operation.
· Power on the system.
3. After I.MX6x enters Polling.Compliance , press the Toggle Button on CLB to select the output , make sure the data waveform is compliance pattern, 5.0GT/s for GEN2, 2.5GT/s for GEN1.
4. Follow the Oscilloscope operation instruction, set it to the right mode.
5. Capture and save at least 1 million * 200 ps of data and clock simultaneously at the sample rate of 50GS/s for GEN2, or 250,000 UI * 400 ps of data at the sample rate of 25GS/s for GEN1.
6. Run free software Sigtest to analyze the PCIE TX signal.
7. Customer could adjust the parameters of the PCIE_PHY by changing IOMUXC_GPR8 register settings to get the test past.
a. The default of this Register is configured as:
imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN1, 0 << 0, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_SWING_FULL, 127 << 18, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_SWING_LOW, 127 << 25, IOMUXC_GPR8);
b. write the Register, Address: 20E_0000h base + 20h offset = 20E_0020h; command:
/unit_tests/memtool -32 0x020e0020= FFFD4000
This document was generated from the following discussion: i.Mx6 PCIe compliance