Presentación Kinetis L - NVIC.pdf

[#1]

Nested Vectored Interrupt Controller Module by Vicente Gómez Freescale TIC.

1. NVIC Explanation
2. Hands-on
   1. IRQ using a pin.
   2. Interruption timers.

Presentación de la NVIC (Nested Vectored Interrupt Controller) por Vicente Gómez, Freescale TIC.

1. Explicación de la NVIC.
2. Hands-On
   1. IRQ usando un pin.
   2. Timers con interrupción

[Hiroki]

Hi,

I'd like to know why the cycle number of tail-chaining is 11 cycle.

I have not been able to find the document of this reasoning.

Why does Cortex-M0+ need 11 cycle for tail-chaining in spite of 6 cycles for Cortex-M4?

Best Regards,

Hiroki