i.MX6DL LPDDR2 Support for L3.0.35_4.0.0

Document created by JackLee1z Employee on Jun 6, 2013Last modified by JackLee1z Employee on Oct 28, 2013
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This patch release is target for LPDDR2 ( dual channels in interleave mode ) support on i.MX6DL platform. Two patches are prepared to modify u-boot and kernel in order to have correct DRAM init sequence, 400MHz & 24MHz frequency switching and suspend/resume support.

 

The patches are not fully verified. It is provided as reference for customer to enable their i.MX6DL board with LPDDR2. Customization and Testing is needed by customer.

 

We need to remind some points here:

 

  • MMDC_MDCFG3LP in 24MHz need to increase the margin ( 0x40222 -> 0x80555 ) in order to pass the OS frequency switch stress test. We are identifying the reason but this workaround is working fine and included to the patch.
  • Code changes in kernel is prepared so that it is compatible to DDR3. In other words, the DDR type will be detected and a correct handling will be done for LPDDR2 and DDR3.
  • In LPDDR2 system, we can't put SDQ pin into LPM during suspend. Otherwise, the system cannot resume.
  • Dual channels in fix mapping mode is not recommended to use.
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