i.MX 6Solo LPDDR2 Registry Settings

Document created by Mark Middleton Employee on May 8, 2013
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Issue: On i.MX 6Solo designs using LPDD2 memory, the correct settings for two important registries may be confusing to determine.

 

Solution:

 

1) MMDCx_MDMISC register, LPDDR2_2CH Field: For the i.MX 6Solo processor, this field should always be set to '0'.

 

Reason: Two channel mode is not possible on this processor. Only channel MMDC0 is connected to external pins.

 

2) IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET register, DDR_SEL Field: For the i.MX 6Solo processor, this field should always be set to "00".

 

Reason: A DRAM Warm Reset requires a response from MMDC1, which is not connected externally on the 6Solo processor, so a Warm Reset never complets.

 

These two issues will be clarified in a subsequent revision of the MCIMX6SDL Reference Manual.

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