i.MX6SL EPDC QoS

Document created by MaxTsai Employee on May 31, 2019Last modified by MaxTsai Employee on Jul 8, 2019
Version 2Show Document
  • View in full screen mode

Why raising QoS priority for EPDC

Eink has been developing higher resolution panel. With higher resolution, TCE underrun problem is observed more easily. Highest QoS priority can provide obvious improvement.

 

What's TCE underrun

TCE is Timing Controller Engine which is responsible for TFT scan frame refreshes. The pixel FIFO (PIX_FIFO) is used to load working buffer pixel data for TCE. When FIFO underrun, TCE_UNDERRUN_IRQ interrupt is triggered, and TCE underrun log pops up in kernel log.

The pixel data is processed by TCE to generate TFT voltage control pixels for panel. If an underrun occurs, unknown data is used and that can damage the panel.

About the patch

The patch raises EPDC reading to highest priority (QoS='f'), so the EPDC reading becomes real time channel in MMDC configuration. The patch is based on L4.1.15 kernel. Stress test of unit test can pass with 1920x1440 configuration.

Outcomes