Flash layout for new boot flow with TF-A

Document created by Swati Gupta Employee on Feb 15, 2019Last modified by Swati Gupta Employee on Nov 4, 2019
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Please note that the LSDK memory layout for TF-A boot flow explained in this topic is only applicable for LSDK 18.12 and newer releases. 

The following table shows the memory layout of various firmware stored in NOR/NAND/QSPI flash device or SD card on all QorIQ Reference Design Boards.

When the board boots from NOR flash, the NOR bank from which the board boots is considered as the "current bank" and the other bank is considered as the "alternate bank". For example, if LS1043ARDB boots from NOR bank 4, to update an image on NOR bank 0, you need to use the "alternate bank" address range,0x64000000 - 0x64F00000.
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                
Firmware DefinitionMaxSizeFlash Offset (QSPI/NAND flash)Absolute address (NOR bank 0 on LS1043ARDB, LS1021ATWR)

Absolute address 

(NOR bank 4 LS1043ARDB, LS1021ATWR)

Absolute address (NOR bank 0 on LS2088ARDB)

Absolute address

(NOR bank 4 on LS2088ARDB)

SD Start Block No.
RCW + PBI + BL2 (bl2.pbl)1 MiB0x000000000x600000000x640000000x580000000

0x584000000

0x00008
ATF FIP Image (fip.bin) BL31 + BL32 + BL334 MiB0x001000000x601000000x641000000x5801000000x5841000000x00800
Boot firmware environment1 MiB0x005000000x605000000x645000000x5805000000x5845000000x02800
Secure boot headers2 MiB0x006000000x606000000x646000000x5806000000x5846000000x03000
Secure header or DDR PHY FW512 KiB0x008000000x608000000x648000000x5808000000x5848000000x04000
Fuse provisioning header512 KiB0x008800000x608800000x648800000x5808800000x5848800000x04400
DPAA1 FMAN ucode256 KiB0x009000000x609000000x649000000x5809000000x5849000000x04800
QE/uQE firmware256 KiB0x009400000x609400000x649400000x5809400000x5849400000x04A00
Ethernet PHY firmware256 KiB0x009800000x609800000x649800000x5809800000x5849800000x04C00
Script for flashing image256 KiB0x009C00000x609C00000x649C00000x5809C00000x5849C00000x04E00
DPAA2-MC or PFE firmware3 MiB0x00A000000x60A000000x64A000000x580A000000x584A000000x05000
DPAA2 DPL1 MiB0x00D000000x60D000000x64D000000x580D000000x584D000000x06800
DPAA2 DPC1 MiB0x00E000000x60E000000x64E000000x580E000000x584E000000x07000
Device tree(needed by uefi)1 MiB0x00F000000x60F000000x64F000000x580F000000x584F000000x07800
Kernellsdk_linux.itb16 MiB0x01000000NANANANA0x08000
Ramdisk rfs32 MiB0x02000000NANANANA0x10000

 

The following figures highlight the changes in the flash layout for previous boot flow (with PPA) and flash layout for TF-A boot flow.

 

Flash layout for previous boot flow (with PPA)

 

 

Changed flash layout for TF-A boot flow

 

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