Example MPC5746R FCCU Alarm State GHS716

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* File:                 main.c
* Owner:            Peter Vlna
* Version:           1.7
* Date:               Oct-10-2017
* Classification: General Business Information
* Brief:                Example contains startup with PLL0 200MHz as system clock
*                          and demonstrates reset triggered on FCCU Alarm state
*                          counter exppire.
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* Test HW:  MPC57xx
* Maskset:  1N83M (cut 2.0B)
* Target :  internal_FLASH
* Fsys:     200MHz PLL0 as system clock
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Revision History:
1.0     Oct-19-2015     Peter Vlna   Initial Version
1.1    Nov-11-2015    Peter Vlna   Added PPL0 200MHz as system clock
1.2    Dec-02-2015    Peter Vlna  Added Flash controller init
1.3    Dec-02-2015    Peter Vlna  Fixed system clock init
1.4    Feb-07-2017    Peter Vlna  SWT0 and SWT1 disabled in startup
1.5     May-31-2017    Peter Vlna  Fixed comments in AC6 (CLKOUT)
1.6     Oct-04-2017    Peter Vlna  Added PIT + Interrupts
1.7    Oct-05-2017    Peter Vlna  FCCU EOUT test in Alarm state with SMC
*******************************************************************************/

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