S32K clock mechanism & configuration

Document created by Fang Li Employee on Jun 22, 2018
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First let us see the clock tree:

Core clock up to 112M, Bus clock up to 56M, Flash clock up to 28M.

Clock can been from: System OSC、Slow IRC 、Fast IRC and System PLL

 

1. OSC
SCG_SOSCCFG

 

2. PLL configuration
formula: SPLL_CLK = (VCO_CLK)/2
VCO_CLK = SOSC_CLK/(PREDIV + 1) *(MULT + 16) 

3. SCG_SPLLCSR

 

void SystemClockInit(void)
{
SCG->SOSCCFG = 0x3C;
SCG->SOSCCSR |= 1<<0; /* SOSCEN=1 enable SOSC clock */
/*wait clock active*/
while((SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0);

SCG->SPLLCSR &= ~(0x1<<0) ; /* SPLLEN=0: disable PLL*/
SCG->SPLLCFG &= ~(0x7<<8); /* PREDIV=0: 1 */
SCG->SPLLCFG |= 0xCU<<16; /* MULT=12: 28   PLL VCO = 8/1*(12+16) = 224M */
SCG->SPLLCSR |= 0x1<<0; /* SPLLEN=1: enable PLL */
/* wait PLL active*/
while((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) == 0);

SCG->RCCR |= SCG_RCCR_DIVCORE(0); /* DIVCORE=0: 1, CORE/SYS_CLK  112MHz */
SCG->RCCR |= SCG_RCCR_DIVBUS(1); /* DIVBUS=1: 2, BUS_CLK  56MHz */
SCG->RCCR |= SCG_RCCR_DIVSLOW(3); /* DIVSLOW=2: 4   FLASH_CLK  is 28MHz */
SCG->RCCR &= 0xFEFFFFFF; /* Initially set to SIRC so that LSB could be set as '0' */
SCG->RCCR |= SCG_RCCR_SCS(6); /* SCS=6: system clock System PLL */
}

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