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* Detailed Description:
* Purpose of the example is to show how to generate Multi-bit or Single-bit ECC
* error in internal RAM (user must choose it in the option at the end of main
* function).
* ECC fault is generated with using of core register E2EECSR. If error injection
* is enabled (E2EECSR0[INVC]=1) and certain mask is set (E2EECSR0[CHKINVT]),
* subsequent write to SRAM creates error in SRAM array.
* When corrupted data is read the IVOR1 exception handler is called in case of
* multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt handler
* is called in case of single-bit ECC error (FCCU interrupt occurs).
* Both function calls MEMU handler.
* The example displays notices in the terminal window (connector J19 on
* MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A).
* No other external connection is required.
* ------------------------------------------------------------------------------
* Test HW: MPC57xx_Motherboard + MPC5744P-144DC
* MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B
* Fsys: 200 MHz PLL with 40 MHz crystal reference
* Debugger: Lauterbach Trace32
* Target: internal_FLASH, RAM
* Terminal: 19200-8-no parity-1 stop bit-no flow control
* EVB connection: default
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