PWM example code for S12ZVL

Document created by Daniel Martynek Employee on May 30, 2017Last modified by ebiz_ws_prod on Dec 13, 2017
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This example shows all the variability in configuration of the S12PWM8B8CV2 PWM module.
Five PWM channels are configured with different clock source, polarity, alignment, period and duty cycle.


Four clock sources (A, B, SA, SB) are derived from bus clock using dividers.


Selected polarity of PWM channel determines its duty-cycle calculation,
whereas the alignment determines its period calculation.


Four 8-bit channels (4-5, 6-7) are concatenated into two 16-bit channels.
Channels 4 and 6 become high-order channels, whereas channels 5 and 7 become low-order channels.
Low order channels configure clock, polarity, alignment and enablement.
Also, these channels (5 and 7) are the output channels routed to a port.
Period and duty-cycle are configured with both low-order and high-order channels.


PWM period registers (PWMPERx) and duty registers (PWMDTYx) are double buffered
so that if they change while the channel is enabled,
the change will not take effect until one of the following occurs:
1. The effective period ends
2. Counter resets
3. The channel is disabled

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