Example MPC5643L eTimer DMA GHS614

File uploaded by Peter Vlna Employee on Apr 12, 2016
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* Detailed Description:

* This example demonstrate DMA transfer triggered by eTimer module compare

* event CMPLD1 load into COMP1. Used is eTimer_0 channel_5.

* It is necessary to configure DREQ[x] register according to channel_5 of

* eTimer_0.

* ------------------------------------------------------------------------------

* Test HW:  MPC57xx

* Maskset:  0N89D

* Target :  SRAM

* Fsys:     120 MHz PLL

*

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Revision History:

1.0     Apr-08-2016     b21190(Vlna Peter)  Initial Version

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