********************************************************************************
* Detailed Description:
* This example demonstrate DMA transfer triggered by eTimer module compare
* event CMPLD1 load into COMP1. Used is eTimer_0 channel_5.
* It is necessary to configure DREQ[x] register according to channel_5 of
* eTimer_0.
* ------------------------------------------------------------------------------
* Test HW: MPC57xx
* Maskset: 0N89D
* Target : SRAM
* Fsys: 120 MHz PLL
*
********************************************************************************
Revision History:
1.0 Apr-08-2016 b21190(Vlna Peter) Initial Version
*******************************************************************************/
