********************************************************************************
* Detailed Description:
*
* LINFlexD_1 configured as Master
* - sends Header
* - either transmits a data to LIN Slave or receives data from a LIN Slave
* - no interrupt is used, just SW pooling
*
* LINFlexD_0 as Slave
* - receives header from a LIN Master
* - either receives data from a LIN Master or transmits a data to Master
* - filter is enabled
* - TX interrupt is used to prepare data to send and
* - RX interrupt to read received data
*
* EVB connection:
*
* Switches on Motherboard:
* P6.1 to P8.1 ... SW1 to PA0
* P6.2 to P8.2 ... SW2 to PA1
* P6.3 to P8.3 ... SW3 to PA2
* P6.4 to P8.4 ... SW4 to PA3
*
* Unconnect LINFlexD_0 from UART transceiver
* J14 SCI_RX open
* J13 SCI_TX open
*
* As only single LIN transceiver is available LINFlex modules are connected
* together before this transceiver in the way TX pins together and RX pins together.
* TX pins must be configured as open drain and use a pullup resistor.
*
* P11.15 to P12.8 TX pins
* P11.16 to P12.7 RX pins
*
* Connect LINFlexD_1 to LIN transceiver on Motherboard
* J17 - LIN_TX ON
* J16 - LIN_RX ON
* J15 - LIN_EN ON
* P3 1-2 ON ... VSUP to 12V
**
* See LIN signal on P3.3 or J4.4.
*
* ------------------------------------------------------------------------------
* Test HW: MPC5744P
* Maskset: 1N65H
* Target : RAM, internal_FLASH
* Fsys: 200 MHz PLL with 40 MHz crystal reference
* Terminal: None
********************************************************************************
Revision History:
1.0 Feb-22-2016 PetrS Initial Version of LIN example
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Original Attachment has been moved to: Example-MPC5744P-LINFlex-LIN-Master-Slave-test-v1_0-GHS614.zip
