Example MPC5777C-1b+2b_RAM_ECC_error_injection GHS614

File uploaded by David Tosenovjan Employee on Sep 17, 2015Last modified by David Tosenovjan Employee on Oct 1, 2015
Version 3Show Document
  • View in full screen mode

********************************************************************************

* Detailed Description:

* Purpose of the example is to show how to generate Multi-bit or Single-bit

* ECC error in internal SRAM (user must choose it in the option at the end of

* main function).

* Error Injection Module is used to generate a non-correctable (or single-bit)

* ECC error in RAM. The bad data is accessed then, so the IVOR1 exception (or

* ERM combined interrupt service routine) is generated and handled.

* Example also offers useful macros for EIM and ERM modules.

* The example displays notices in the terminal window (USBtoUART bridge J21)

* (19200-8-no parity-1 stop bit-no flow control on eSCI_A).

* No other external connection is required.

*

* ------------------------------------------------------------------------------

* Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C

* MCU:             PPC5777CMM03 2N45H CTZZS1521A

* Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz

* Debugger:        Lauterbach Trace32

* Target:          internal_FLASH

* Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A

* EVB connection:  eSCI_A is USBtoUART bridge (connector J21)

*

********************************************************************************

Outcomes