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* Detailed Description:
*
*
* This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules.
* The setting is selected in the way to have a PWM output signal synhronized with
* SWG output signal. This is necessary for resolver usage in motor control appls.
* The CTU_0 is triggered from FlexPWM_0's. The PMWB output rising edge is used here.
* The CTU generates the eTIMER1_TRG signal, that is a trigger signal for the
* SGEN module. The delay between PWMB and SGEN trigger is changed so you can see
* the generated sinusoidal signal change phase against the PWMB output.
*
* See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0,
* AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO).
*
* This example is set for 9.765625KHz SGEN/PWM frequency.
*
* Note because the SGEN trigger input is an asynchronous signal, it must be held high
* for at least 2 SGEN clock cycles in order to capture the input trigger.
* As the CTU generates the trigger as a pulse of single CTU clock width, the CTU clock must be
* half of the SGEN clock at least.
*
* Use the AUX0_clk_DIV0 to test this behaviour.
*
*
* ------------------------------------------------------------------------------
* Test HW: MPC57xx
* Maskset: 1N65H
* Target : internal_FLASH
* Fsys: 200 MHz PLL with 40 MHz crystal reference
*
* EVB connection:
*
* P11.8 - D[7] .. SGEN output
* connected to FEC PHY's MIIMODE input on motherboard,
* to see full amplitude remove J26
*
* P8.12 - A[11] .. FlexPWM A[0] output
* P8.11 - A[10] .. FlexPWM B[0] output
*
*
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