That is correct. The 40mV applies to all kinds of voltage variations.
P5020 supports various power management modes. When less drastic frequency changes are desired, software can switch the CPU to a slower speed PLL, such as 1 GHz versus 1.5 GHz. Many cores could be switched to a slower PLL during periods of light traffic, with the ability to immediately return those cores to the full rate PLL should traffic suddenly increase. The more traditional Power Architecture single core power management modes (Core Doze, Core Nap, Core Sleep) are also available in the e5500.
For P5020, maximum USBx_VDD_1P0 pin current is 10mA per pin (phy).
The 10G interface does not support the magic packet wake-on-LAN feature.