I assume that 50mV specification for P5020 includes all kinds of voltage variations, such as DC regulation, steady-state ripple and transients. Is this correct? I would like to know the maximum current step and slew rate (A/us) for P5020?
That is correct. The 40mV applies to all kinds of voltage variations.
Is dynamic power management such as frequency stepping supported in P5020?
P5020 supports various power management modes. When less drastic frequency changes are desired, software can switch the CPU to a slower speed PLL, such as 1 GHz versus 1.5 GHz. Many cores could be switched to a slower PLL during periods of light traffic, with the ability to immediately return those cores to the full rate PLL should traffic suddenly increase. The more traditional Power Architecture single core power management modes (Core Doze, Core Nap, Core Sleep) are also available in the e5500.
What is the estimated maximum current draw (amps) on the P5020 USBx_VDD_1P0 pin?
For P5020, maximum USBx_VDD_1P0 pin current is 10mA per pin (phy).
Does 10G interface support the magic packet wake-on-LAN feature? The dTSEC chapter clearly states that the dTSEC does, but the 10G chapter in the P5020 RM makes no mention of it.
The 10G interface does not support the magic packet wake-on-LAN feature.