P2040/P2041 Clocking Specific FAQs

Document created by Omar Cruz Lopez Employee on Aug 6, 2012Last modified by Omar Cruz Lopez Employee on Aug 6, 2012
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What is the integrated phase noise jitter requirement for SD_REF_CLK and SYSCLK for P2041?

We don't have the integrated phase noise jitter, the SYSCLK we defined the period jitter and phase noise. For SD_REF_CLK, we follow the PCIe industrial standard spec and it defined peak-to-peak jitters.


What is the PLL loop bandwidth of internal PLL in P2040 which uses 100MHz and 125MHz refclks from system?

The PLL loop bandwidth of internal PLL is >= 500 KHz. The PLL bandwidth varies with many factors including ref clock rate.


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