P1022/P1013 Clocking Specific FAQs

Document created by Omar Cruz Lopez Employee on Aug 6, 2012Last modified by Omar Cruz Lopez Employee on Aug 6, 2012
Version 2Show Document
  • View in full screen mode

For P1013/22, what is the maximum bit rate clock for SSI? Is it really 12.285MHz or can it be run up to platform clock / 8?

Maximum bit rate clock for SSI is as per hardware spec i.e. 12.285MHz. This is the maximum speed at which the SSI IP is guaranteed to work.

From a system perspective it is possible to clock it at a higher speed, but for P1013 that is not supported.

If platform clock is 400MHz, please use appropriate values of DIV2, PSR and PM to ensure that the bit rate clock for SSI does not exceed 12.285MHz.

 

Can you please confirm that the P1022 ethernet input clock is actually 2 clocks: one for each eTSEC, with name TSECn_GTX_CLK125/GPIOm? The p1022 ballmap spreadsheet only shows one gtx_clk125 pin (like the 8536), but the current data sheet (Revision E) indicates there are two.

The ball map shows only primary functions of a pin. By default both the eTSECs would share the same clock i.e TSEC1_GTX_CLK125 @Y29. If required, user can opt to use separate clock for eTSEC2 . The separate clock for eTSEC2 is multiplexed with TSEC_1588_TRIG_IN1@AH27 and can be configured using PMUXCR[6:7].


The SD card spec requires SD clock to supply for at least 74 clock cycles. On the other hand, the eSDHC controller in P1022 supplies about 13 SD clock cycles (with 180 degrees phase shift) at power up. Will SD card have any reliability issue by this fewer clock cycles than what is required by spec?

No, SD card should not have the reliability issue. 74 clocks can be supplied by setting SYSCTL [INITA]. The 180 degree phase shift will not affect card or eSDHC IP block's operation. The phase shift is due to the synchronizer.




Attachments

    Outcomes