I would like to know if output signals of blocks which are not clocked during sleep mode are driven or not. For example, are eTSEC2 RGMII signals driven during sleep mode?
Yes, they would be driven but there would be no activity on them. Please note that this is for "sleep" mode NOT "deep sleep"
P1022 supports “Wake on LAN” from the Deep Sleep. If TSEC operates via SGMII it needs for SVDD,XVDD, SVDD2,VDD2, SDAVDD and SDAVDD2 (SGMII power). All these powers are switchable in the Deep Sleep. Can we leave these rails powered in the Deep Sleep and expect that the P1022 will support “Wake on LAN” via SGMII?
Serdes is powered down during deep sleep, so Wake up on LAN is not supported for Deep Sleep in SGMII mode. Wake on LAN is supported for RGMII. Please note only eTSEC1 supports this feature. (Assuming eSTEC1 and eTSEC2 as the nomenclature)
Are there any pull-downs for signals POWER_EN and ASLEEP on the P1022 board? Is BVDD switched off using POWER_EN?
LOE has pull down via 4.7k ohms resistor as POR config. LWE has neither pull-up nor pull-down. Yes, BVdd is switched off using POWER_EN.
What is the difference between P1022 and P1013 in terms of power dissipation and power management?
In P1013 the Power supply pins for second core do need to be tied to their respective levels (although you can miss off the PLL filter for the unused core supply). So even when the second core is not used, it is powered. With TEST_SEL tied low (tie directly to ground) the second core is disabled and there should be no chance of accidental execution of code by second core.