Can the 8543 support the 16bit FIFO by combining the eTSEC1 pins with the GPIO pins that would otherwise be assigned to eTSEC2 in MPC8548?
It is recommended for the unused I/O pins (such as the MECC [0:7]) to be pull down to GND via a 10k resistor. 8543 can, in fact, operate in 16-bit FIFO mode on eTSEC1. The key is to differentiate "signal functionality" from "logic resources." 8543 offers the logic for eTSEC1 and eTSEC3, but all the same signals are still there (including the signals otherwise used for eTSEC2). You'll notice that the references you note (T14-129, T14-173, Section C.2) all clearly make reference to "eTSEC2 signals". According to first bullet in section C.2 - "What signal functionality is NOT included in 8543: - eTSEC2 controller signals. Exceptions to this are when a) the signals are used as GPIO signals, or b) the signals are used to accommodate eTSEC1 in 16-bit FIFO mode."
What will the value of GPOUT[0:7] be when they are disabled by GPIOCR? all 0? All 1? or all Hi-Z?
GPOUT[0:7] pins are tristated if they are not enabled.