MPC8541 PCIe Specific FAQs

Document created by Omar Cruz Lopez Employee on Jul 31, 2012Last modified by Omar Cruz Lopez Employee on Jul 31, 2012
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Does the PCIe controller go to D3 hot state automatically if the user does not configure any registers? Should the external device be in D3 hot state explicitly before MPC8541 goes to sleep mode?

PCIe controller will not go to D3 hot state automatically. Software has to write Powerstate field of PMCSR register. If the downstream component is in D3 hot state, then permissible states for Upstream component are D0-D3hot. Refer Section 5.3.2 of Base specification 1.0a The Bus states are L1 or L2/L3 Ready if the power is going to be removed. The procedure for entry into these states is described in Section 5.3.2.1 and 5.3.2.3


What internal interrupt numbers are assigned to PCIe1 through PCIe3 in MPC8541?

All PCIe interrupts in MPC8541 are error interrupts and are ORed with other error interrupts to result in "Error" which is mapped to #0 of the OPIC.


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