MPC8541 DDR Specific FAQs

Document created by Omar Cruz Lopez Employee on Jul 31, 2012
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For MPC8541, when I am using a DDR controller with a 64-bit interface with a 32-bit memory sub system, which lanes should I use?

When a 64-bit DDR interface is configured in a 32-bit data bus width, lanes [0:3] (MDQ [0:31]) will be used.


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