Can MPC8541 GPIO signals drive LEDs directly? What is the output current requirement (Iol / Ioh) for GPIO signals?
Yes, MPC8541 GPIO signals can drive LEDs directly. When GPIO is driven HIGH, to maintain a voltage of 2.4V, no more than 2mA should be drawn from the IO and conversely to maintain a 0.4V when GPIO is driven LOW no more than 2mA should be sunk into the IO.
Current limiting would have to be done through external resistors. Below are the current and voltage requirements:
@3.3V Input high voltage VIH 2V Input low voltage VIL 0.8V Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA2 Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4V Output low voltage (OVDD = min, IOL = 2 mA) VOL 0.4V
@2.5V Input high voltage VIH 1.7V Input low voltage VIL 0.7V Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA2 Output high voltage (OVDD = min, IOH = –2 mA) VOH 1.7V Output low voltage (OVDD = min, IOL = 2 mA) VOL 0.7V
@1.8V Input high voltage VIH 1.2V Input low voltage VIL 0.6V Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA2 Output high voltage (OVDD = min, IOH = –0.5 mA) VOH 1.35V Output low voltage (OVDD = min, IOL = 0.5 mA) VOL 0.4V
MPC8541EC revision F defines output delay time for eSDHC interface in table 52. Is there any specification regarding "output hold" time? If not, how should I consider about it?
The min value of Output delay time becomes the output hold. ( Half clock period - |min khov| ) becomes the input hold for the receiver chip.
How is the selection between eLBC and DIU signals done in MPC8541? Is it done through SPI signals? Why are SPI signals "-" in data phase of 16-bit GPCM?
Selection between eLBC and DIU signals is done via PMUXCR [eLBC_DIU], and INDEPENDENTLY selection between eSPI, eLBC or eSDHC signals is done via PMUXCR[SPI_eLBC].
Thus for SPI signals user only needs to use PMUXCR[SPI_eLBC]. And for 32-bit GPCM user has to set BOTH PMUXCR[eLBC_DIU] and PMUXCR[SPI_eLBC].
Using the TDM interface in shared mode (Tx clk and sync are used for Tx and Rx), are pullups / pulldowns required for TDM_RCK and TDM_RFS in MPC8541?
Actually the multiplexing happens at the SoC level and the selection of shared mode happens at the IP level, hence pins would not automatically revert to GPIO. It is recommended to be pulled to OVdd by 2k-10k.
Can you please describe the procedure for timer soft reset and reconfiguration for MPC8541?
Software must do the following before asserting TMR_CTRL[TMSR]: 1) Place the controller in graceful transmit stop (DMACTL[GTS]=1, wait for IEVENTGn[GTSC]=1) 2) Disable receive (MACCFG1[RX_EN]=0) Note: After setting timer soft reset (TMR_CTRL[TMSR]), software must leave the bit high for at least three 1588 reference clocks or tx_clk cycles, whichever is slower, before clearing the bit.
How should I handle 2 CKSTP_OUT signals for MPC8541? Note 11 on Table 1 in the MPC8541EC states that these need a weak pullup resistor. However, Table 4-13 in the MPC8541RM shows that these 2 signal default to 1 (as part of cfg_rom_loc). Do these pins need pullups?
The internal pull up for por_cfg pins is only for the duration when HRESET is asserted. So after POR pull up will be required. For handling this kind of a situation a tri state buffer with Enable tied to HRESET can be used. Add pull down at buffer input and pull up at buffer output.
While HRESET is asserted, the pull down is visible on the buffer output. After HRESET deassertion, buffer output is tri stated and pull up on the output of buffer pulls up the CKSTP_OUT signal.
What is the default value of POWER_EN pin in EXTEST and on BYPASS/IDCODE mode in MPC8541?
Default values in modes for EXTEST and BYPASS/IDCODE: 1) EXTEST Normally SAMPLE-PRELOAD is run prior to the EXTEST instruction whose purpose is to configure BIDI PADS either as input or output. In this state we shift the value in BSR chain so depending upon value shifted in BSR this pin would have that value. 2) IDCODE and BYPASS Pin is at the functional value. These instructions don’t have any effect on the pin value.