MPC8535 DDR Specific FAQs

Document created by Omar Cruz Employee on Jul 31, 2012Last modified by Omar Cruz Employee on Jul 31, 2012
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Is it correct that TIMING_CFG_5[RODT_ON] and TIMING_CFG_5[RODT_OFF] do not affect internal ODT circuit for MPC8535? These values are always set in u-boot for our DDR3 based boards (e.g. P2020DS, MPC8569MDS). However external ODT is never enabled for SDRAM reads, this could lead to a conclusion that internal ODT is also affected by the TIMING_CFG_5 setting. Can you comment?

TIMING_CFG_5 register is only for DRAM ODT (external ODT), this is verified and confirmed. As for your suggestion that because in most cases the read ODT on DRAM is off and hence it has something to do with internal ODT is not a valid assumption. The Read ODT for DRAM is an option available if required. In most cases it will not apply, but there may be a configuration that may require it and then the option is available for such users.

Please clarify the meaning of TIMING_CFG_5 register for DDR3 controller of the MPC8535. The sentence ".. relevant ODT signal(s)" is common to all fields. What is this referring to? Is that both a) an internal signal controlling internal IOs (enabled by CFG_2[ODT_CFG]) and b) the external MODT[] signals going to the SDRAM? If yes, what is the delay between the assertion of the internal ODT signal (e.g. set by TIMING_CFG_5[RODT_ON])and actual switching of the internal RTT?

These are related to the ODT timings to the DRAM. If ODT during reads is not used, then the RODT_ON and RODT_OFF values can be cleared. These are the ODT signal turn ON/OFF latency. For DDR3 it is defined as WL-2=CWL+AL-2. If one DIMM slot is used then there is no need for dynamic ODT setting.