MPC8535 Clocking Specific FAQs

Document created by Omar Cruz Employee on Jul 31, 2012
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MPC8535 PCI controller can get clock from SYSCLK (synchronous) or from PCICLK (PCI asynchronous mode). If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCICLK, otherwise the processor will not boot up. Is this limit just due to PCI bus specs and if PCI is not used then MPC8535 PCI block can withstand 125MHz in synchronous mode?

The PCI input clock frequency spec range is between 33 - 66MHz. IF the PCI interface is enabled, then this spec here will matter regardless whether you are running in synchronous or asynchronous mode. IF the PCI is disabled / un-used, it will not matter what input clock is being fed into this interface. Also, please refer to section 15.2 of the 8535 bring-up guide for termination details of the PCI pins including the PCI1_CLK pin when the interface is not being used.

I am starting 8535 design making use of both SerDes serial interfaces: 1) SerDes1: PCI Express 1 (x4) (2.5 Gbps) → SerDes1 Lanes A-D; PCI Express 2 (x1) (2.5 Gbps) → SerDes1 Lanes E-F 2) SerDes2: SATA1 → SerDes2 Lane A. Each SerDes has its own reference clock. They will both run at 100MHz. Are there any phase requirements between these 2 clocks?

There is no requirement on 8535 for any particular phase relationship between reference clock for Serdes 1 vs Serdes 2 because each serdes is completely independent.