MPC8308 DDR Specific FAQs

Document created by Omar Cruz Lopez Employee on Jul 31, 2012
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Please specify the DDR read only and write only counters for MPC8308.

Event 19 counts DDR reads only while event 27 counts DDR writes only in MPC8308.


How are DDR errors cleared in the ESUMR reg (bit 8)? Do they need to re-init the DDR?

You need to clear the ERR_DEFECT [MBE] bit (write 1 to clear). After that the ESUMR bit 8 will be cleared.


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