MPC8306/MPC8306S QUICC Engine Specific FAQs

Document created by Omar Cruz Lopez Employee on Jul 31, 2012Last modified by Omar Cruz Lopez Employee on Jul 31, 2012
Version 2Show Document
  • View in full screen mode

Is there any suggested approach to determining the tx/rx ring buffer sizes on the peripherals that interface to the UCC? How can I decide on the ring size? The bandwidth would be 45 Mbps. The MTU on the serial interface can range up to 16k Bytes.

Even if MTU could be 16K bytes, the average frame could be much smaller. Find out the average frame size and pick up a buffer size that is bit larger than the average frame size. This usually creates a good balance of efficiency between processing time and memory usage. It is much more efficient in terms of processing time to process a frame of 16K in one BD/Buffer of 16K size than in 16 BDs/Buffers of 1K size. However, if all buffers are 16K size while 90% of the frames are 1K, most memory is wasted.

Generally, the ring size should be equal to the number of BD’s required to accommodate the largest possible frame size + 4 extra BDs. However, over here the bandwidth is relatively high (45M) and could be quite bursty. Hence we would suggest starting with "TWO largest possible frame size + 4 extra BDs"


P1016 Hardware spec says that the QUICC engine periodically polls its Rx/Tx rings and if a BD is not empty, checks the ownership flag and moves to the next step. How does the user application trigger/control the QE to start polling?

For TX BD ring, (after configured) QE will periodically poll the ring and process the BD that is not empty and then move to next BD. When a BD is actually transmitted, a "transmission complete" event (and interrupt if enabled) will be generated, so the BD/Buffer can be released.

For RX BD ring, (after configured) QE will pre-fetch a BD and then process the BD when data is received. When a packet (frame) is received, a "received" event (and interrupt if enabled) will be generated, so the BD/Buffer can be released/processed. If no empty BD is available during the pre-fetch, an "out-of-BD" error will be reported.


After MPC8306 QE reset, when cores enables transmitter but BD is not ready, what signal will be on the line - IDLE(0XFF) or flags(7E)? Can this signal be configured?

Yes, it should be configured by GUMR[RTSM].



Attachments

    Outcomes