When setting the ABSWP bit (in LBCR) in P1020, are the address bytes swapped or just mirrored? Also, can you confirm that the LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash?
By setting ABSWP bit (i.e. ABSWP=1), if address=0x12345678. Then LAD [0:15] = 0x7856 and LA[16:31]=0x5678. LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash
What is NAND Flash controller speed and size for P1011?
AeLBC can work at 83 MHz. At minimum twc, it can be equal to 2 LCLK i.e. half the frequency of LCLK. The maximum page size supported by eLBC is 2K.
If I use one mck to drive all 5 ddr3-chips in P1011, can I use the leveling function? Also, which topology do you recommend for this?
Yes, writing leveling function should be used to compensate the additional flight time skew delay between different chips introduced by fly-by topology. However, we do not recommend routing the clock in fly-by topology while address, command and control signals routed by other topology. For more detail of JEDEC DDR3 routing topology, please visit [www.JEDEC.org].
Is a 32-bit data interface the only way to control whether or not ABSWP applies (i.e. ABSWP affects 8 and 16-bit data interfaces but does not affect 32-bit data interfaces)?
ABSWP also affects 32-bit interface and it is not advisable to set ABSWP for 32 bit interface as only 16 LSB address gets visible on LAD[0:15] and zeroes are output on the LAD[16:31].