i.MX6 maximum EIM burst length and performance

Document created by Yuri Muhin Employee on Jul 21, 2015
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  When considering EIM bursts (performance, burst length, etc) we should

take into account, that some parameters (maximum burst length, which

defines length in clocks of back-to-back EIM access) depend on master, which

performs the access (EIM always service as slave). The EIM can split a master
burst in order to meet own settings, but the EIM cannot join two master accesses.

So, the maximum  burst length is defined by master. 

Usually three options are applied for EIM burst accesses :

- ARM block copy instructions (LDM / STM) ;
- ARM NEON copy instructions (VLDM / VSTM) ;

- i.MX SDMA.


  Below are some details regarding these options.  


1. ARM.

ARM provide recommendations below about the fastest way to copy memory on a Cortex-A8.


  According to section 8.1.2 (Supported AXI transfers) of ARM Cortex-A9 Technical Reference
Manual, it is possible to get maximum 64 bytes (16 beats x 4 bytes) burst for read and

8 bytes burst for write.



“INCR N (N:1-16) 32-bit read transfers

INCR N (N:1-2) for 32-bit write transfers”






2. SDMA.

  According to section (Burst DMA Unit) of the i.MX6 DQ RM :

“Perform up to 8-beat read and write bursts to the ARM platform memory, which

optimizes throughput when accessing SDRAM-type devices because of an internal,

36-byte FIFO”.

This means, that burst length of the SDMA cannot be greater than 32 bytes

(8 beat x 4 bytes).


As for performance and implementation of SDMA approach, please look at the following :


“Measure SDMA Memory To Memory Copy Performance on i.MX6Q”



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