Example MPC5675K-2b_RAM+2b_FLASH_ECC_error_injection CW210

File uploaded by David Tosenovjan Employee on Jun 4, 2015
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* Detailed Description:

* Purpose of the example is to show how to generate Multi bit ECC error in

* internal SRAM or FLASH (user can choose it in the option at the end of main

* function) and how to handle this error with respect to constraints given by

* MPC5675K architecture (ECSM/RGM/FCCU relation and ECC error handling through

* reset). The example is only possible to run in internal_FLASH target. Power-

* -on-reset is required after downloading the code into MCU's flash. The example

* displays notices in the terminal window (setting specified below). No other

* external connection is required.

* Example also shows impact of enabled cache (macro OPTIMIZATIONS_ON).

*

* ------------------------------------------------------------------------------

* Test HW:        MPC5675KEVB

* MCU:            PPC5675KFMMSJ in Lock-Step mode

* Fsys:           180/150 MHz CORE_CLK

* Debugger:       Lauterbach Trace32

*                 PeMicro USB-ML-PPCNEXUS

* Target:         RAM, internal_FLASH

* Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A

* EVB connection: default

*

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