Example MPC5674F_1b+2b_RAM_ECC_error_injection CW210

File uploaded by David Tosenovjan Employee on Jun 4, 2015
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* Detailed Description:


* ECSM Error Generation Register EEGR is used to generate a non-correctable

* or single bit ECC error in RAM. The bad data is accessed then, so the IVOR1

* exception is generated and handled.

* This file shows also ECSM_combined_isr and how to correct the wrong data.

* Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be

* injected by DMA read or CPU read.

* At the end of main file you can choose if single bit or multi bit is injected

* and select particular ME/EE setup by comment/uncomment of particular function

* calls.


* ------------------------------------------------------------------------------

* Test HW:   XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B

* MCU:       PPC5674FMVYA264

* Terminal:  19200-8-no parity-1 stop bit-no flow control on eSCI_A

* Fsys:      264/200/150/60 MHz