Example MPC5634M_2b_RAM_ECC_error_injection CW210

File uploaded by David Tosenovjan Employee on Oct 9, 2014Last modified by David Tosenovjan Employee on Dec 9, 2015
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* Detailed Description:

* ECSM Error Generation Register EEGR is used to generate a non-correctable ECC

* error in RAM. The bad data is accessed then, so the IVOR1 exception is

* generated and handled.

* This file shows also ECSM_combined_isr and how to correct the wrong data.

* Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be

* injected by DMA read or CPU read.

* At the end of main file you can select particular ME/EE setup by

* comment/uncomment of particular function calls.


* ------------------------------------------------------------------------------

* Test HW:        XPC563MKIT

* MCU:            PPC5633MMLQ80

* Fsys:           80/60/40/12 MHz

* Debugger:       Lauterbach Trace32

*                 PeMicro USB-ML-PPCNEXUS

* Target:         RAM, internal_FLASH

* Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A

* EVB connection: default