I have been doing some memory-to-memory DMA tests on the i.MX RT 1020 and found that I could transfer between OCRAM, ITC and DTC in any combination.
To see what happened I also tried transferring from QSPI Flash memory to one of these internal RAM areas, expecting that there would be an error However it also worked.
How is this possible? Does the DMA transfer attempt trigger a read from the QSPI Flash stall until ready, and then performs the transfer? Is it really as clever as that or is there another explanation?
I measured the time it took to perform a DMA transfer of 1024 bytes (long word transfer units) between the 4 areas:
OCRAM -> OCRAM 26.36us
OCRAM -> ITC 26.8us
OCRAM -> DTC 24.36us
ITC -> OCRAM 28.44us
ITC -> ITC 26.36us
ITC -> DTC 26.36us
DTC -> OCRAM 28.44us
DTC -> ITC 26.36us
DTC -> DTC 26.36us
QSPI-Flash (125MHz) -> OCRAM 40.95us
QSPI-Flash (125MHz) -> ITC 38.93us
QSPI-Flash (125MHz) -> DTC 38.93us
QSPI-Flash (125MHz) -> QSPI-Flash (125MHz) 159.5us
All transfers resulted with the an accurate copy of the source image at the destination after the transfer had completed, apart from the final case where no change resulted in the QSPI-Flash; however the DMA transfer did not terminate with an error.
Can anyone comment on the transfer speeds? When I repeat the test the results are always exactly the same (the times include the time to set up the DMA transfer [around 15us] as well as the actual data copy). I have the Cortex M7 core clocked at 500MHz, IPG 125MHz and FlexSPI 125MHz. Cache is disabled and code is from QSPI-Flash. And in particular the QSPI Flash results (how does it even work????)!