Hi All
Looking at the routine to enable data cache (__STATIC_INLINE void SCB_EnableDCache (void)) I find this line of code:
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
According to the comment it is selecting data cache but according to the ARM documentation it is selecting instruction cache:
Therefore is the code wrong or is the comment wrong?
Regards
Mark
Hi Mark Butcher ，
Thanks for your question.
You can check the same ARM cortex M7 core document: ARM® Cortex®-M7 Devices Generic User Guide, you will find the following description:
So, even the ARM document example comment, it also comment select leve 1, I think maybe it is the ARM document problem, you also can check it with the ARM side.
About your second question:
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With the code as it is it invalidated
- 128 sets 4 ways.
If I select data cache instead (according to ARM documentation) it invalidates
- 256 sets 2 ways.
According to NXP "The data cache is 4-way set-associative and instruction cache is 2-way set-associative with cache line size of 32 bytes"
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Please tell me the detail ARM document page, and the NXP document page, then I can help you to check it.
Have a great day,
Kerry
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Hi Kerry
I now believe that there is an error in the ARM document but it is strange that the error is 5 years old and I haven't found any reference to anyone pointing it out anywhere.
It is not a problem with the LEVEL but with selecting whether the ID register reflects the instruction of the data setting.
This is the document loaded directly form the ARM web site yesterday [ARM® Cortex®-M7 Processor
Revision r0p2 Technical Reference Manual]:
Here it clearly states that InD needs to be set to 1 to select data cache yet the NXP code and my experiments show that it is the other way round.
In the document that you reference "ARM Cortex-M7 Devices - Generic User Guide" one finds it inverted:
which matches with the example code and also the code in the CMSIS routine, which is used by NXP.
Code thus looks correct (and reacts I believe correctly) but the ARM technical reference manual seems to be wrong.
Regards
Mark
Kerry
I did a bit more research and have found a newer version of the technical reference manual "r1p2"
with change-note:
Therefore it was a documentation error. I will use exclusively the newest version from now (ARM is still linking the older one at some locations at infocenter.arm)!!
Regards
Mark
Hi Mark Butcher,
Thanks for your double confirmation.
Yes, you are right, ARM side really have a lot of document version.
Anyway, just use the newest document.
But when you fund the ARM document error, you also can report it to ARM side.
Have a great day,
Kerry
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