Kinetis Design Studio USB "3TR Timeout!" in khci.c

rhana · ‎08-25-2014

Hello,

At the moment I am working with host_msd_fatfs_frdmk22f120m_bm (but attempting to run this on an MK22FN1MOVLQ12. The system has been tested with other USB projects in CodeWarrior 10.6 so I know it works.) I can get debug messages through RS-232, and after I put in a USB stick I will get this output:

USB file system test

Waiting for USB mass storage to be attached...

3TR Timeout!

The USB vectors are the same, so I would expect any interrupts from the USB module to work without issue.The register values in the USB module

show activity.

in khci.c the message is generated here inside usb_khci_task(), and after detecting "usb_host_ptr->device_attached" is true:

else if (( tr_state == KHCI_TR_TRANSMITING))

{

if (curr_msg.pipe_desc->pipetype != USB_INTERRUPT_PIPE)

{

if ((_usb_khci_get_total_frame_count(usb_host_ptr) - curr_msg.frame) > TIMEOUT_OTHER )

{

res = KHCI_ATOM_TR_BUS_TIMEOUT;

tr_state = KHCI_TR_TRANSMIT_DONE;

done_msg = curr_msg;

printf("3TR Timeout!\n");

return;

}

Any idea on what could be happening? Am I correct in assuming that the MK22F51212 code for USB should run on an MK22FN1MOVLQ12?

Thanks.

JCRib · ‎11-24-2014

Hi everyone,

Problem solved!!!! :smileyhappy:

I'm now able to work with USB stacks V4.1.1 and KSDK USB host examples on a MK22FX512VLK12.

You just need to disable MPU!!!!

1) If you are using KSDK, add MPU definitions to MK22F512 header file. If you are using USB V4.1.1 you can skip this point.

2) Disable MPU - (MPU_CESR = 0)

MPU definitions

/* ----------------------------------------------------------------------------

-- MPU

---------------------------------------------------------------------------- */

/*!

* @addtogroup MPU_Peripheral MPU

* @{

*/

/** MPU - Peripheral register structure */

typedef struct MPU_MemMap {

uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */

uint8_t RESERVED_0[12];

struct { /* offset: 0x10, array step: 0x8 */

uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */

uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */

} SP[5];

uint8_t RESERVED_1[968];

uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */

uint8_t RESERVED_2[832];

uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */

} volatile *MPU_MemMapPtr;

/* ----------------------------------------------------------------------------

-- MPU - Register accessor macros

---------------------------------------------------------------------------- */

/*!

* @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros

* @{

*/

/* MPU - Register accessors */

#define MPU_CESR_REG(base) ((base)->CESR)

#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)

#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)

#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])

#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])

/*!

* @}

*/ /* end of group MPU_Register_Accessor_Macros */

/* ----------------------------------------------------------------------------

-- MPU Register Masks

---------------------------------------------------------------------------- */

/*!

* @addtogroup MPU_Register_Masks MPU Register Masks

* @{

*/

/* CESR Bit Fields */

#define MPU_CESR_VLD_MASK 0x1u

#define MPU_CESR_VLD_SHIFT 0

#define MPU_CESR_NRGD_MASK 0xF00u

#define MPU_CESR_NRGD_SHIFT 8

#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)

#define MPU_CESR_NSP_MASK 0xF000u

#define MPU_CESR_NSP_SHIFT 12

#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)

#define MPU_CESR_HRL_MASK 0xF0000u

#define MPU_CESR_HRL_SHIFT 16

#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)

#define MPU_CESR_SPERR_MASK 0xF8000000u

#define MPU_CESR_SPERR_SHIFT 27

#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)

/* EAR Bit Fields */

#define MPU_EAR_EADDR_MASK 0xFFFFFFFFu

#define MPU_EAR_EADDR_SHIFT 0

#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)

/* EDR Bit Fields */

#define MPU_EDR_ERW_MASK 0x1u

#define MPU_EDR_ERW_SHIFT 0

#define MPU_EDR_EATTR_MASK 0xEu

#define MPU_EDR_EATTR_SHIFT 1

#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)

#define MPU_EDR_EMN_MASK 0xF0u

#define MPU_EDR_EMN_SHIFT 4

#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)

#define MPU_EDR_EPID_MASK 0xFF00u

#define MPU_EDR_EPID_SHIFT 8

#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)

#define MPU_EDR_EACD_MASK 0xFFFF0000u

#define MPU_EDR_EACD_SHIFT 16

#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)

/* WORD Bit Fields */

#define MPU_WORD_VLD_MASK 0x1u

#define MPU_WORD_VLD_SHIFT 0

#define MPU_WORD_M0UM_MASK 0x7u

#define MPU_WORD_M0UM_SHIFT 0

#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)

#define MPU_WORD_M0SM_MASK 0x18u

#define MPU_WORD_M0SM_SHIFT 3

#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)

#define MPU_WORD_M0PE_MASK 0x20u

#define MPU_WORD_M0PE_SHIFT 5

#define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u

#define MPU_WORD_ENDADDR_SHIFT 5

#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)

#define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u

#define MPU_WORD_SRTADDR_SHIFT 5

#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)

#define MPU_WORD_M1UM_MASK 0x1C0u

#define MPU_WORD_M1UM_SHIFT 6

#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)

#define MPU_WORD_M1SM_MASK 0x600u

#define MPU_WORD_M1SM_SHIFT 9

#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)

#define MPU_WORD_M1PE_MASK 0x800u

#define MPU_WORD_M1PE_SHIFT 11

#define MPU_WORD_M2UM_MASK 0x7000u

#define MPU_WORD_M2UM_SHIFT 12

#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)

#define MPU_WORD_M2SM_MASK 0x18000u

#define MPU_WORD_M2SM_SHIFT 15

#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)

#define MPU_WORD_PIDMASK_MASK 0xFF0000u

#define MPU_WORD_PIDMASK_SHIFT 16

#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)

#define MPU_WORD_M2PE_MASK 0x20000u

#define MPU_WORD_M2PE_SHIFT 17

#define MPU_WORD_M3UM_MASK 0x1C0000u

#define MPU_WORD_M3UM_SHIFT 18

#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)

#define MPU_WORD_M3SM_MASK 0x600000u

#define MPU_WORD_M3SM_SHIFT 21

#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)

#define MPU_WORD_M3PE_MASK 0x800000u

#define MPU_WORD_M3PE_SHIFT 23

#define MPU_WORD_PID_MASK 0xFF000000u

#define MPU_WORD_PID_SHIFT 24

#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)

#define MPU_WORD_M4WE_MASK 0x1000000u

#define MPU_WORD_M4WE_SHIFT 24

#define MPU_WORD_M4RE_MASK 0x2000000u

#define MPU_WORD_M4RE_SHIFT 25

#define MPU_WORD_M5WE_MASK 0x4000000u

#define MPU_WORD_M5WE_SHIFT 26

#define MPU_WORD_M5RE_MASK 0x8000000u

#define MPU_WORD_M5RE_SHIFT 27

#define MPU_WORD_M6WE_MASK 0x10000000u

#define MPU_WORD_M6WE_SHIFT 28

#define MPU_WORD_M6RE_MASK 0x20000000u

#define MPU_WORD_M6RE_SHIFT 29

#define MPU_WORD_M7WE_MASK 0x40000000u

#define MPU_WORD_M7WE_SHIFT 30

#define MPU_WORD_M7RE_MASK 0x80000000u

#define MPU_WORD_M7RE_SHIFT 31

/* RGDAAC Bit Fields */

#define MPU_RGDAAC_M0UM_MASK 0x7u

#define MPU_RGDAAC_M0UM_SHIFT 0

#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)

#define MPU_RGDAAC_M0SM_MASK 0x18u

#define MPU_RGDAAC_M0SM_SHIFT 3

#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)

#define MPU_RGDAAC_M0PE_MASK 0x20u

#define MPU_RGDAAC_M0PE_SHIFT 5

#define MPU_RGDAAC_M1UM_MASK 0x1C0u

#define MPU_RGDAAC_M1UM_SHIFT 6

#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)

#define MPU_RGDAAC_M1SM_MASK 0x600u

#define MPU_RGDAAC_M1SM_SHIFT 9

#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)

#define MPU_RGDAAC_M1PE_MASK 0x800u

#define MPU_RGDAAC_M1PE_SHIFT 11

#define MPU_RGDAAC_M2UM_MASK 0x7000u

#define MPU_RGDAAC_M2UM_SHIFT 12

#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)

#define MPU_RGDAAC_M2SM_MASK 0x18000u

#define MPU_RGDAAC_M2SM_SHIFT 15

#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)

#define MPU_RGDAAC_M2PE_MASK 0x20000u

#define MPU_RGDAAC_M2PE_SHIFT 17

#define MPU_RGDAAC_M3UM_MASK 0x1C0000u

#define MPU_RGDAAC_M3UM_SHIFT 18

#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)

#define MPU_RGDAAC_M3SM_MASK 0x600000u

#define MPU_RGDAAC_M3SM_SHIFT 21

#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)

#define MPU_RGDAAC_M3PE_MASK 0x800000u

#define MPU_RGDAAC_M3PE_SHIFT 23

#define MPU_RGDAAC_M4WE_MASK 0x1000000u

#define MPU_RGDAAC_M4WE_SHIFT 24

#define MPU_RGDAAC_M4RE_MASK 0x2000000u

#define MPU_RGDAAC_M4RE_SHIFT 25

#define MPU_RGDAAC_M5WE_MASK 0x4000000u

#define MPU_RGDAAC_M5WE_SHIFT 26

#define MPU_RGDAAC_M5RE_MASK 0x8000000u

#define MPU_RGDAAC_M5RE_SHIFT 27

#define MPU_RGDAAC_M6WE_MASK 0x10000000u

#define MPU_RGDAAC_M6WE_SHIFT 28

#define MPU_RGDAAC_M6RE_MASK 0x20000000u

#define MPU_RGDAAC_M6RE_SHIFT 29

#define MPU_RGDAAC_M7WE_MASK 0x40000000u

#define MPU_RGDAAC_M7WE_SHIFT 30

#define MPU_RGDAAC_M7RE_MASK 0x80000000u

#define MPU_RGDAAC_M7RE_SHIFT 31

/*!

* @}

*/ /* end of group MPU_Register_Masks */

/* MPU - Peripheral instance base addresses */

/** Peripheral MPU base pointer */

#define MPU_BASE_PTR ((MPU_MemMapPtr)0x4000D000u)

/** Array initializer of MPU peripheral base pointers */

#define MPU_BASE_PTRS { MPU_BASE_PTR }

/* ----------------------------------------------------------------------------

-- MPU - Register accessor macros

---------------------------------------------------------------------------- */

/*!

* @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros

* @{

*/

/* MPU - Register instance definitions */

/* MPU */

#define MPU_CESR MPU_CESR_REG(MPU_BASE_PTR)

#define MPU_EAR0 MPU_EAR_REG(MPU_BASE_PTR,0)

#define MPU_EDR0 MPU_EDR_REG(MPU_BASE_PTR,0)

#define MPU_EAR1 MPU_EAR_REG(MPU_BASE_PTR,1)

#define MPU_EDR1 MPU_EDR_REG(MPU_BASE_PTR,1)

#define MPU_EAR2 MPU_EAR_REG(MPU_BASE_PTR,2)

#define MPU_EDR2 MPU_EDR_REG(MPU_BASE_PTR,2)

#define MPU_EAR3 MPU_EAR_REG(MPU_BASE_PTR,3)

#define MPU_EDR3 MPU_EDR_REG(MPU_BASE_PTR,3)

#define MPU_EAR4 MPU_EAR_REG(MPU_BASE_PTR,4)

#define MPU_EDR4 MPU_EDR_REG(MPU_BASE_PTR,4)

#define MPU_RGD0_WORD0 MPU_WORD_REG(MPU_BASE_PTR,0,0)

#define MPU_RGD0_WORD1 MPU_WORD_REG(MPU_BASE_PTR,0,1)

#define MPU_RGD0_WORD2 MPU_WORD_REG(MPU_BASE_PTR,0,2)

#define MPU_RGD0_WORD3 MPU_WORD_REG(MPU_BASE_PTR,0,3)

#define MPU_RGD1_WORD0 MPU_WORD_REG(MPU_BASE_PTR,1,0)

#define MPU_RGD1_WORD1 MPU_WORD_REG(MPU_BASE_PTR,1,1)

#define MPU_RGD1_WORD2 MPU_WORD_REG(MPU_BASE_PTR,1,2)

#define MPU_RGD1_WORD3 MPU_WORD_REG(MPU_BASE_PTR,1,3)

#define MPU_RGD2_WORD0 MPU_WORD_REG(MPU_BASE_PTR,2,0)

#define MPU_RGD2_WORD1 MPU_WORD_REG(MPU_BASE_PTR,2,1)

#define MPU_RGD2_WORD2 MPU_WORD_REG(MPU_BASE_PTR,2,2)

#define MPU_RGD2_WORD3 MPU_WORD_REG(MPU_BASE_PTR,2,3)

#define MPU_RGD3_WORD0 MPU_WORD_REG(MPU_BASE_PTR,3,0)

#define MPU_RGD3_WORD1 MPU_WORD_REG(MPU_BASE_PTR,3,1)

#define MPU_RGD3_WORD2 MPU_WORD_REG(MPU_BASE_PTR,3,2)

#define MPU_RGD3_WORD3 MPU_WORD_REG(MPU_BASE_PTR,3,3)

#define MPU_RGD4_WORD0 MPU_WORD_REG(MPU_BASE_PTR,4,0)

#define MPU_RGD4_WORD1 MPU_WORD_REG(MPU_BASE_PTR,4,1)

#define MPU_RGD4_WORD2 MPU_WORD_REG(MPU_BASE_PTR,4,2)

#define MPU_RGD4_WORD3 MPU_WORD_REG(MPU_BASE_PTR,4,3)

#define MPU_RGD5_WORD0 MPU_WORD_REG(MPU_BASE_PTR,5,0)

#define MPU_RGD5_WORD1 MPU_WORD_REG(MPU_BASE_PTR,5,1)

#define MPU_RGD5_WORD2 MPU_WORD_REG(MPU_BASE_PTR,5,2)

#define MPU_RGD5_WORD3 MPU_WORD_REG(MPU_BASE_PTR,5,3)

#define MPU_RGD6_WORD0 MPU_WORD_REG(MPU_BASE_PTR,6,0)

#define MPU_RGD6_WORD1 MPU_WORD_REG(MPU_BASE_PTR,6,1)

#define MPU_RGD6_WORD2 MPU_WORD_REG(MPU_BASE_PTR,6,2)

#define MPU_RGD6_WORD3 MPU_WORD_REG(MPU_BASE_PTR,6,3)

#define MPU_RGD7_WORD0 MPU_WORD_REG(MPU_BASE_PTR,7,0)

#define MPU_RGD7_WORD1 MPU_WORD_REG(MPU_BASE_PTR,7,1)

#define MPU_RGD7_WORD2 MPU_WORD_REG(MPU_BASE_PTR,7,2)

#define MPU_RGD7_WORD3 MPU_WORD_REG(MPU_BASE_PTR,7,3)

#define MPU_RGD8_WORD0 MPU_WORD_REG(MPU_BASE_PTR,8,0)

#define MPU_RGD8_WORD1 MPU_WORD_REG(MPU_BASE_PTR,8,1)

#define MPU_RGD8_WORD2 MPU_WORD_REG(MPU_BASE_PTR,8,2)

#define MPU_RGD8_WORD3 MPU_WORD_REG(MPU_BASE_PTR,8,3)

#define MPU_RGD9_WORD0 MPU_WORD_REG(MPU_BASE_PTR,9,0)

#define MPU_RGD9_WORD1 MPU_WORD_REG(MPU_BASE_PTR,9,1)

#define MPU_RGD9_WORD2 MPU_WORD_REG(MPU_BASE_PTR,9,2)

#define MPU_RGD9_WORD3 MPU_WORD_REG(MPU_BASE_PTR,9,3)

#define MPU_RGD10_WORD0 MPU_WORD_REG(MPU_BASE_PTR,10,0)

#define MPU_RGD10_WORD1 MPU_WORD_REG(MPU_BASE_PTR,10,1)

#define MPU_RGD10_WORD2 MPU_WORD_REG(MPU_BASE_PTR,10,2)

#define MPU_RGD10_WORD3 MPU_WORD_REG(MPU_BASE_PTR,10,3)

#define MPU_RGD11_WORD0 MPU_WORD_REG(MPU_BASE_PTR,11,0)

#define MPU_RGD11_WORD1 MPU_WORD_REG(MPU_BASE_PTR,11,1)

#define MPU_RGD11_WORD2 MPU_WORD_REG(MPU_BASE_PTR,11,2)

#define MPU_RGD11_WORD3 MPU_WORD_REG(MPU_BASE_PTR,11,3)

#define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU_BASE_PTR,0)

#define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU_BASE_PTR,1)

#define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU_BASE_PTR,2)

#define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU_BASE_PTR,3)

#define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU_BASE_PTR,4)

#define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU_BASE_PTR,5)

#define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU_BASE_PTR,6)

#define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU_BASE_PTR,7)

#define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU_BASE_PTR,8)

#define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU_BASE_PTR,9)

#define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU_BASE_PTR,10)

#define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU_BASE_PTR,11)

/* MPU - Register array accessors */

#define MPU_EAR(index) MPU_EAR_REG(MPU_BASE_PTR,index)

#define MPU_EDR(index) MPU_EDR_REG(MPU_BASE_PTR,index)

#define MPU_WORD(index,index2) MPU_WORD_REG(MPU_BASE_PTR,index,index2)

#define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU_BASE_PTR,index)

/*!

* @}

*/ /* end of group MPU_Register_Accessor_Macros */

/*!

* @}

*/ /* end of group MPU_Peripheral */

Best regards,

José Ribeiro

ghecu · ‎12-19-2017

Hi Jose,

Did you ran it on eval twr board?

I try to work it out for a friend on his custom board and window always failed to recognize it (USB malfunction message).

Giac.

vikashkumar · ‎05-08-2017

Hey Jose,

We are also trying to port the USB stack from K22xx512 to K22FN1Mxx. We came across your post and disabled the MPU accordingly. We are able to get the attach/detach events as required.

We just wanted to know how disabling MPU affects the USB events/interrupts as we are trying to integrate the stack further to ucosii environment.

Vikash.

JCRib · ‎11-19-2014

Hello,

I'm having exactly the same problem, porting the USB stack 5.0 to MK22FX512VLK12 (which belongs to the same family as MK22FN1MOVLQ12).

It gives me a 3TR Timeout message.

Can it be related to time fuctions? RTC or PIT? I don't have the RTC crystal on my board. Is it needed?

Hana, do you have the 32.768KHz RTC crystal on your board? BTW, did you get it working on USB stack v4?

Best regards,

Jose

BlackNight · ‎11-22-2014

I have the USB stack (USB CDC for the moment) running without problems on my sumo robot hardware with the MK22FX512VLK12 (http://mcuoneclipse.com/2014/10/30/new-sumo-robot-assembled-and-looking-good/, http://mcuoneclipse.com/2014/07/26/zumo-robot-with-wifi-and-gps/).

I'm using an improved version of the Freescale V4.1.1 stack as Processor Expert component and this one runs fine on a variety of Kinetis, ColdFire and S08 USB devices. Unfortunately I cannot test the MSD host mode as my board does not support host mode.

You might try that USB stack with your board in MSD host mode (see USB MSD Host for the Freedom Board | MCU on Eclipse for a tutorial for the FRDM-KL25Z board).

I hope this helps,

Erich

rhana · ‎08-26-2014

The "3TR Timeout!" is also occurring on the host_hid_mouse demo for the twrk22f120m.

These are the only two demos I have tested so far with the MK22FN1MOVQ12.

It looks like there are differences in USB registers also between the k22FN1MOVQ12 and the MK22F51212 in the following:

USBx_ADDINFO 7-3 IRQNUM

USBx_USBTRC0 4-3

Also the K22F51212 has 4 new registers:

USBx_CLK_RECOVER_INT_STATUS

USBx_CLK_RECOVER_INT_EN

USBx_CLK_RECOVER_IRC_EN

USBx_CLK_RECOVER_CTRL

On a higher level, what is causing this "3TR Timeout!" message?

Rick_Li · ‎08-28-2014

Hi, just got feedback from Application Engineer on this issue.

as replied, usually, the 3TR issue is caused by the signal quality, can you try another USB Stick?

Since I dont have frdmk22f120m on my side at present, I will order one for testing.

JCRib · ‎11-22-2014

Hello,

I'm having the same problem on a K22 1st generation MK22FX512 which belongs to the same family as MK22FN1M0 that Robert is using. I tried the same code on the Freedom board and it works!

Differences between my board and Freedom:

1) MK22FX512 instead of MK22FN512

2) no 32K crystal

I checked USB signal on the oscilloscope and they are fine! 83ns bit time and sending messages every 1ms.

The same error occures using USB Stack v5 bare metal or KSDK examples.

rhana · ‎08-28-2014

A few points to consider:

1. HID mouse example gives us the same problem. We run into the same problem with the host_hid_mouse_twrk22f120m_bm example (the result is identical, so this problem is not isolated to USB stick types.)

2. The same message appears when plugging a USB stick into the HID Mouse example, and likewise plugging a mouse into the USB Stick example.

3. We have verified USB works on our system (with another demo application from USB v.4.1.1), so the signal integrity is not likely an issue.

And as I mentioned before we are attempting to run this on an MK22FN1MOVLQ12.

Rick_Li · ‎08-28-2014

I will contact the USB Stack Appliation engineer for further assistance and will keep you informed!

I'm sorry for this inconvenience has caused to you!

rhana · ‎08-25-2014

Enabling more debugging commands in the USB... the output looks more like this:

USB file system test

Waiting for USB mass storage to be attached...

usb_dev_list_attach_device attach device_usb_khci_open_pipe_usb_host_ch9_get_des

criptorusb_host_ch9_dev_requsb_hostdev_validateusb_hostdev_validate SUCCESSFUL_u

sb_host_unregister_serviceusb_host_ch9_dev_req SUCCESSFULusb_host_send_setupusb_

hostdev_validateusb_hostdev_validate SUCCESSFUL_usb_host_link_trusb_host_send_se

tup SUCCESSFUL_usb_host_ch9_get_descriptor, SUCCESSFULusb_dev_list_attach_device

SUCCESSFUL3TR Timeout!

I don't see any failure messages. Detaching the USB Stick yields more SUCCESSFUL debug messages.