AnsweredAssumed Answered

i.MX6 ECSPI single burst transfers

Question asked by jeffrey coffman on Jul 18, 2013
Latest reply on Mar 17, 2016 by jayakumar2



I am trying to interface a SPI NOR flash (slave) to my i.MX6 (master).  My device requires that the CS be held for the entire transaction (cmd byte + N data bytes returned from the device), however when I observe the spi transfer on my logic analyzer I noticed that the i.MX6 releases CS between each data word.  My device will not shift out its data in this case.


I should mention I am using spidev, and that I've tried setting cs_change in the spi_transfer and that had no effect...  Looking in spi_imx.c I don't see where the cs_change parameter is ever used.


It appears from the code in spi_imx.c that the ecspi controller should be set up todo a single burst transfer for the bus I am using (ecspi3) as shown in figure 21-8 of the IMX6DQRM.  However I am seeing behavior more like figure 21-9 on my logic analyzer even though SS_CTL[3:0] is appears correct and SMC is cleared.  So I don't understand whats going on at this point.


Can some i.MX6 spi expert chim in?