iMXRT1176 SDRAM initialisation via DCD (wait)

[mjbcswitzerland]

Hi All

I notice that the NXP reference DCD for SDRAM iitialisation as used by the i.MX RT 1176 deviates from the method used for all other parts that i have seen in the way that it waits after issuing commands.

Usually there is a command issued, like PRECHARGE ALL (by writing the command to the SEMC_IPCMD command register). Then there is a wait loop checking the IPCMDDONE flag.

In the case of the i.MX RT 1176 there is instead a sequence of 5 NOPs written instead.

Here is an extract from the dcd.c file in the SDK reference.

/* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */

0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,

/* #8, command: nop */

0xC0, 0x00, 0x04, 0x00,

/* #9, command: nop */

0xC0, 0x00, 0x04, 0x00,

/* #10, command: nop */

0xC0, 0x00, 0x04, 0x00,

/* #11, command: nop */

0xC0, 0x00, 0x04, 0x00,

/* #12, command: nop */

0xC0, 0x00, 0x04, 0x00,

What is the reason for this? I would expect that the same wait loop would be suitable but is it possible that there is an issue doing this (errata for example?) and therefore it should be avoided?

Many thanks in advance

Regards

Mark


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[jingpan]

Hi @mjbcswitzerland ,

It seems when trying to use 0xCF to check 2 bits, the SDRAM can't work, so it use NOP to instead of it. And it is still not clear why using 0xCF to check 2 bits will cause error.

I think we can use 0xCF to check IPCMDDONE bit only, as RT1050 SDK.

Regards,

Jing

[mjbcswitzerland]

Hi Jing

What is the second bit that should be checked? I would expect that checking just IPCMDDONE would be adequate.

If two bits are to be waited on maybe using 0xCF twice would be suitable - first to wait for the first flag and then to wait for the second flag?

In any case I have understood that possibly the ROM loader (which I presume is responsible for interpreting the 0xCF wait) may be the issue.

Regards

Mark

[jingpan]

Hi @mjbcswitzerland ,

ROM will also check IPCMDERR.

Regards,

jing