Hello,
We are using a i.MX RT controller for eMMC application development.
we are facing some clock related issues for USDHC driver as below
a) What should be the reset value of PFD0_FRAC parameter in register CCM_ANALOG_PFD_528n ?
Observations: after power on the MCU before any system / clock initializations, we have read the CCM_ANALOG_PFD_528n register value in debug mode and get the value of PFD0_FRAC = 0 (000000b) but as per datasheet reset value of this field should be 0x1B.(011011b)
b) As per IMXRT1064RM (reference manual) document, base clock for the SDCLK frequency generation is ipg_perclk, but in example driver code for SDMMC, USDHC_CLK_ROOT is used to derive SDCLK frequency. Should we consider ipg_perclk or USDHC_CLK_ROOT for SDCLK configurations.
Thanks,
Deep D.
Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
a) a) What should be the reset value of the PFD0_FRAC parameter in register CCM_ANALOG_PFD_528n?
-- The reset value of the PFD0_FRAC should be 0x0C, as it should be in the range of 12~35.
b) As per IMXRT1064RM (reference manual) document, base clock for the SDCLK frequency generation is ipg_perclk, but in example driver code for SDMMC, USDHC_CLK_ROOT is used to derive SDCLK frequency. Should we consider ipg_perclk or USDHC_CLK_ROOT for SDCLK configurations?
-- As the below figure shows, the ipg_clk_perclk is generated from the usdhcn_clk_root.
Have a great day,
TIC
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Hello jeremyzhou,
Thanks for the quick response.
a) -- The reset value of the PFD0_FRAC should be 0x0C, as it should be in the range of 12~35.
Yes, the range of PFD0_FRAC is from 12~15 , but as per reference manual reset value of this register should be 0x1b. (please refer screenshot of this register reset value from reference manual in above question).
Also, when we read this register value just after power on before clock initialization using debug mode, it is showing as 0x00. below is the screen shot of this register captured in debug mode at start up before clock initialization. (value of PFD2_FRAC is as per the reference manual)
b) -- As the below figure shows, the ipg_clk_perclk is generated from the usdhcn_clk_root.
In our project, ipg_clk_perclk is set to 75 MHz while usdhc1_clk_root is set to 198 MHz. In this case, which base frequency should be considered for clock generation of SDCLK.
Is there any specific application note available for USDHC driver, it would be really helpful to understand USDHC driver in more detail.
Thanks,
Deep darji
Hi，
Thanks for your reply.
1) I've no idea with your screenshot, just as the below figure shows, the value of the CCM_ANALOG_PFD_528 conforms to the description of the RM.
2) Is there any specific application note available for USDHC driver, it would be really helpful to understand USDHC driver in more detail.
-- No, there's no similar application note.
Have a great day,
TIC
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